IP Library Granted Patent US 8,927,410
Granted Patent B2
US 8,927,410 · App. 14/100,893 · Granted Jan 6, 2015

Methods of forming through substrate interconnects

Inventors: Dave Pratt (Meridian, ID); Andy Perkins (Boise, ID)
Assignee: Micron Technology, Inc.
H01L21/76898
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Quick Facts
Patent No.
US 8,927,410
App. No.
14/100,893
Granted
Jan 6, 2015
Kind
B2
Abstract

A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Claims (28)

1. A method of forming a through substrate interconnect, comprising:

forming a passivation dielectric over a back-side of a semiconductor substrate;

after forming the passivation dielectric, etching through the passivation dielectric and then into semiconductive material of the substrate from the substrate back-side to form a via;

applying a liquid dielectric over the passivation dielectric and into the via to line only an elevationally outermost portion of sidewalls of the via;

solidifying the liquid dielectric within the via;

vapor depositing a dielectric material to within the via to line over the solidified dielectric within the via and to line over sidewall portions of the via received elevationally inward of the solidified dielectric within the via; and

forming conductive material within the via over the vapor deposited dielectric material and forming a through substrate interconnect with the conductive material.

2. The method of claim 1 wherein the liquid and solidified dielectric within the via lines no more than 50% of a combined elevational thickness of the passivation dielectric and the semiconductive material that forms the via.

3. The method of claim 1 wherein the solidified dielectric is thicker than the vapor deposited dielectric material.

4. The method of claim 1 wherein the liquid dielectric has a solidified coefficient of thermal expansion which is between that of the passivation dielectric and the vapor deposited dielectric.

5. The method of claim 1 wherein the vapor deposited dielectric material completely covers all sidewalls of the via elevationally inward of the solidified dielectric that is within the via.

6. The method of claim 5 wherein the via has a base, the vapor deposited dielectric material completely covering all of the via base.

7. The method of claim 6 wherein the liquid dielectric has a solidified coefficient of thermal expansion which is between that of the passivation dielectric and the vapor deposited dielectric.

8. The method of claim 1 wherein the via has a base, the vapor deposited dielectric material not completely covering at least one of a) all sidewall of the via, and b) all of the base.

9. A method of forming a through substrate interconnect, comprising:

forming a passivation dielectric over a front-side of a semiconductor substrate;

after forming the passivation dielectric, etching through the passivation dielectric and then into semiconductive material of the substrate from the substrate front-side to form a via;

applying a liquid dielectric over the passivation dielectric and into the via to line only an elevationally outermost portion of sidewalls of the via;

solidifying the liquid dielectric within the via;

vapor depositing a dielectric material to within the via to line over the solidified dielectric within the via and to line over sidewall portions of the via received elevationally inward of the solidified dielectric within the via; and

forming conductive material within the via over the vapor deposited dielectric material and forming a through substrate interconnect with the conductive material.

10. The method of claim 9 wherein the liquid and solidified dielectric within the via lines no more than 50% of a combined elevational thickness of the passivation dielectric and the semiconductive material that forms the via.

11. The method of claim 9 wherein the solidified dielectric is thicker than the vapor deposited dielectric material.

12. The method of claim 9 wherein the liquid dielectric has a solidified coefficient of thermal expansion which is between that of the passivation dielectric and the vapor deposited dielectric.

13. The method of claim 9 wherein the vapor deposited dielectric material completely covers all sidewalls of the via elevationally inward of the solidified dielectric that is within the via.

14. The method of claim 13 wherein the via has a base, the vapor deposited dielectric material completely covering all of the via base.

15. The method of claim 14 wherein the liquid dielectric has a solidified coefficient of thermal expansion which is between that of the passivation dielectric and the vapor deposited dielectric.

16. The method of claim 9 wherein the via has a base, the vapor deposited dielectric material not completely covering at least one of a) all sidewall of the via, and b) all of the base.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (3)
Division 13248970 · Sep 29, 2011
Division 11840120 · Aug 16, 2007
Related Publication 20140099786A1 · Apr 10, 2014