Apparatuses and methods for refreshing memory cells of a semiconductor device
View Patent ↗Apparatuses and methods for refreshing memory cells of semiconductor device are described. An example apparatus includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.
1. An apparatus comprising:
a memory cell array including a plurality of groups of memory cells defined independently by a plurality of first addresses, respectively;
a first control circuit configured to generate a plurality of first refresh signals one after another at first intervals responsive to a self-refresh command and produce a plurality of second addresses one after another at the first intervals responsive to the first refresh signals, respectively; and
a second control circuit configured to be reset responsive to the self-refresh command and provide a control signal when the second control circuit detects that the plurality of second addresses has covered all of the plurality of first addresses since the second control circuit was reset;
wherein the first control circuit is further configured to change lengths of the first intervals responsive to the control signal.
2. The apparatus of claim 1 , wherein the second control circuit includes a counter circuit configured to count a number of the plurality of first refresh signals which have been received at the counter circuit, reset the number responsive to the self-refresh command and provide the control signal when the number exceeds a total number of the plurality of first addresses.
3. The apparatus of claim 2 , wherein the first control circuit includes an additional counter circuit configured to count the number of the plurality of first refresh signals which have been received at the additional counter circuit and not to be reset irrespective of the self-refresh command.
4. The apparatus of claim 1 , wherein the first control circuit includes an oscillator circuit configured to output a plurality of second refresh signals at additional intervals one after another responsive to the self-refresh command and be changed in driving capability responsive to the control signal so that lengths of the additional intervals are changed, the plurality of first refresh signals being produced based on the plurality of second refresh signals.
5. The apparatus of claim 4 , wherein the first control circuit further includes a frequency divider circuit configured to provide a plurality of third refresh signals produced by dividing the plurality of second refresh signals and select the plurality of second refresh signals or the plurality of third refresh signals as the first refresh signals based on a temperature signal.
6. The apparatus of claim 1 , wherein the first control circuit includes a counter circuit configured to count a number of the plurality of first refresh signals to produce the plurality of second addresses, each of the second addresses comprising a plurality of address bits; and
wherein the second control circuit includes a determination circuit configured to receive one of the plurality of address bits of each of the second addresses and determine that the plurality of second addresses has covered all of the plurality of first addresses since the second control circuit was reset when one of the plurality of address bits changes in logic level multiple times.
7. The apparatus of claim 6 , wherein the determination circuit is further configured to receive a most significant bit of each of the second addresses and determine that the plurality of second addresses has covered all of the plurality of first addresses since the second control circuit was reset when the most significant bit changes twice.
8. The apparatus of claim 6 , wherein the first control circuit includes an oscillator circuit configured to output a plurality of second refresh signals one after another responsive to the self-refresh command and be changed in driving capability responsive to the control signal, the plurality of first refresh signals being produced based on the plurality of second refresh signals.
9. The apparatus of claim 8 , wherein the first control circuit further includes a frequency divider circuit configured to provide a plurality of third refresh signals produced by dividing the plurality of second refresh signals and select the plurality of second refresh signals or the plurality of third refresh signals as the first refresh signals based on a temperature signal.