IP Library Granted Patent US 10,134,741
Granted Patent B2
US 10,134,741 · App. 15/652,724 · Granted Nov 20, 2018

Methods of forming an elevationally extending conductor laterally between a pair of conductive lines

Inventors: Guangjun Yang (Meridian, ID); Russell A. Benson (Boise, ID); Brent Gilgen (Boise, ID); Alex J. Schrinsky (Boise, ID); Sanh D. Tang (Kuna, ID); Si-Woo Lee (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/10885H01L21/7682H01L21/76816H01L21/76877H01L27/10814H01L27/10855
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Quick Facts
Patent No.
US 10,134,741
App. No.
15/652,724
Granted
Nov 20, 2018
Kind
B2
Abstract

A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

Claims (60)

1. A method comprising:

forming a conductive line over a semiconductor substrate such that the conductive line extends in a first direction crossing a second direction, the first conductive line including a first side surface extending vertically with respect to the semiconductor substrate, and the semiconductor substrate including a first diffusion region;

forming a sacrificial layer over the conductive line and the semiconductor substrate;

selectively removing the sacrificial layer to leave first sacrificial material over a first part of the first side surface of the conductive line and to expose a portion of the first diffusion region;

forming conductor material such that the conductor material continuously extends in the second direction to pass across the conductive line and to form a conductive portion that is in electrical contact with the portion of the first diffusion region, the conductive portion being isolated from the first part of the first side surface of the conductive line by the first sacrificial material; and

removing the first sacrificial material while keeping the conductor material continuously extending in the second direction to form a first void space between the conductive portion of the conductor material and the first part of the first side surface of the first conductive line.

2. The method of claim 1 , further comprising:

before forming the sacrificial layer, forming sidewall dielectric material over the first part of the first side surface of the conductive line so that the sidewall dielectric material intervenes between the first part of the first side surface of the conductive line and the first void space.

3. The method of claim 1 , wherein the conductive line is capped with dielectric material so that the cap dielectric material intervenes between the conductive line and the conductor material.

4. The method of claim 3 , further comprising:

etching back the conductor material until a part of the dielectric material is exposed while leaving the conductive portion.

5. The method of claim 1 , further comprising:

selectively removing the conductor material to leave some of the conductor material, the some of the conductor material comprising the conductive portion.

6. The method of claim 5 , further comprising:

forming a capacitor in electrical contact with the some of the conductor material.

7. The method of claim 5 ,

wherein the semiconductor substrate further includes a second diffusion region;

wherein the method further comprises forming a buried access line in the semiconductor substrate such that the buried access line defines a channel region between the first and second diffusion regions; and

wherein the conductive line is formed as a bit line in electrical contact with the second diffusion region.

8. The method of claim 1 ,

wherein the sacrificial layer is selectively removed to further include second sacrificial material over a second part of the first side surface of the conductive line;

wherein the forming conductor material comprises:

forming a conductor layer over an entire surface; and

patterning the conductor layer so that the second sacrificial material is exposed while keeping the first sacrificial material covered with the conductor material; and

wherein the removing the first sacrificial material comprises subjecting the exposed second sacrificial material to an etchant for the first sacrificial material.

9. The method of claim 8 , wherein the first sacrificial material is removed by the etchant reaching the first sacrificial material through the second sacrificial material.

10. The method of 9 , further comprising:

after removing the first sacrificial material, selectively removing the conductor material to leave some of the conductor material, the some of the conductor material comprising the conductive portion and the removing the conductor material opening the first void space; and

forming dielectric material to re-seal the first void space.

11. The method of claim 10 , further comprising:

forming conductive material in electrical contact with the conductive portion.

12. The method of claim 1 ,

wherein the sacrificial layer is selectively removed to further include second sacrificial material over a second part of the first side surface of the conductive line;

wherein the method further comprises:

before forming the conductor material, forming first dielectric material to define an area in which the conductor material is to be formed; and

after forming the conductor material, selectively removing the first dielectric material to expose the second sacrificial material while keeping the first sacrificial material covered with the conductor material; and

wherein the removing the first sacrificial material comprises subjecting the exposed second sacrificial material to an etchant for the first sacrificial material.

13. The method of claim 12 , wherein the first sacrificial material is removed by the etchant reaching the first sacrificial material through the second sacrificial material.

14. The method of claim 13 , further comprising:

after removing the first sacrificial material, forming second dielectric material to fill a space that has been formed by removing the first dielectric material.

15. The method of claim 14 , further comprising:

after forming the second dielectric material, selectively removing the conductor material to leave some of the conductor material, the some of the conductor material comprising the conductive portion and the removing the conductor material opening the first void space; and

forming third dielectric material to cover a top of the first void space.

16. The method of claim 15 , further comprising:

forming conductive material in electrical contact with the conductive portion.

17. The method of claim 1 ,

wherein the method further comprises:

before forming the sacrificial layer, forming first dielectric material extending in the second direction to cross across the conductive line so that the sacrificial layer is formed over the conductive line, the semiconductor substrate and the first dielectric material, the first dielectric material including a second side surface extending vertically with respect to the semiconductor substrate;

wherein the sacrificial layer is selectively removed to further include second sacrificial material over a second part of the second side surface of the first dielectric material, the second sacrificial material merging with the first sacrificial material;

wherein the method further comprises:

after forming the conductor material, selectively removing the first dielectric material to expose at least a part of the second sacrificial material; and

wherein the removing the first sacrificial material comprises subjecting the exposed part of the second sacrificial material to an etchant for the first sacrificial material.

18. The method of claim 17 , wherein the first sacrificial material is removed by the etchant reaching the first sacrificial material through the second sacrificial material.

19. The method of claim 18 , further comprising:

forming second dielectric material to fill a space that has been formed by selectively removing the first dielectric material.

20. The method of claim 19 , further comprising:

after forming the second dielectric material, selectively removing the conductor material to leave some of the conductor material, the some of the conductor material comprising the conductive portion and the removing the conductor material opening the first void space; and

forming third dielectric material to cover a top of the first void space.

21. The method of claim 20 , further comprising:

forming conductive material in electrical contact with the conductive portion.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
Continuity (2)
Continuation 15210511 · Jul 14, 2016
Related Publication 20180019245A1 · Jan 18, 2018