Semiconductor memory device including output buffer

1. A memory module comprising:

a module substrate;

a first plurality of memory chips mounted on the module substrate, the first plurality of memory chips including:

a first memory chip;

a second memory chip; and

a group of third memory chips, wherein the second memory chip is arranged between the first memory chip and the group of third memory chips;

a first line pattern provided on the module substrate, the first line pattern extending along the first plurality of memory chips, the first line pattern including:

a first branching point coupled to the first memory chip;

a second branching point coupled to the second memory chip;

a group of third branching points coupled respectively to the group of third memory chips, wherein the second branching point is arranged between the first branching point and the group of the third branching points; and

a fourth branching point arranged between the first branching point and the second branching point; and

a first termination resistor arranged between the first memory chip and the second memory chip and mounted on the module substrate, the first termination resistor including a first end coupled to a terminal power source and a second end,

wherein the fourth branching point is coupled to the second end of the first termination resistor.

2. The memory module, of claim 1 , further comprising a register chip mounted the module substrate, the register chip being coupled to the first line pattern.

3. The memory module of claim 2 , wherein the group of third memory chips are disposed between the second memory chip and the register chip.

4. The memory module of claim 3 , wherein the first plurality of memory chips, the first termination resistor and the register chip are arranged in line.

5. The memory module of claim 1 , wherein the module substrate includes a first principal surface and a second principal surface opposite to the first principal surface;

wherein the first plurality of memory chips and the first termination resistor are mounted on the first principal surface of the module substrate,

wherein the memory module further comprises a second plurality of memory chips mounted on the second principal surface of the module substrate, the second plurality of memory chips including:

a fourth memory chip coupled to the first branching point of the first line pattern;

a fifth memory chip coupled to the second branching point of the first line pattern; and

a group of sixth memory chips coupled respectively to group of the third branching points of the first line pattern, and

wherein the fifth memory chip is arranged between the fourth memory chip and the group of sixth memory chips.

6. The memory module of claim 5 , further comprising a register chip mounted on the first principal surface of the module substrate and coupled to the first line pattern,

wherein the group of third memory chips are disposed between the second memory chip and the register chip.

7. The memory module of claim 6 , wherein the first memory chip and the fourth memory chip are aligned in mounted position with intervention of the module substrate, wherein the second memory chip and the fifth memory chip are aligned in mounted position with intervention of the module substrate, and wherein the group of third memory chips and the group of sixth memory chips are aligned in mounted position with intervention of the module substrate, respectively.

8. The memory module of claim 7 , further comprising a second termination resistor mounted on the second principal surface of the module substrate, the second termination resistor being arranged between the fourth memory chip and the fifth memory chip, the second termination resistor including a third end coupled to the terminal power source and a fourth end coupled to the fourth branching point of the first line pattern.

9. The memory module of claim 1 , further comprising:

a second line pattern provided on the module substrate and coupled to the first line pattern, the second line pattern including:

a fifth branching point; and

a plurality of sixth branching points arranged between the first branching point and a coupling point of the first line pattern and the second line pattern;

a second plurality of memory chips mounted on the module substrate, the second plurality of memory chips being coupled respectively to the plurality of sixth branching points of the second line pattern; and

a second termination resistor mounted on the module substrate, the second termination resistor including:

a third end coupled to the terminal power source; and

a fourth end coupled to the fifth branching point of the second line pattern.

10. The memory module of claim 9 , further comprising a register chip mounted on the module substrate, the register chip being coupled to the coupling point of the first line pattern and the second line pattern.

11. The memory module of claim 10 , wherein the group of third memory chips are disposed between the second memory chip and the register chip;

wherein the module substrate includes a first side edge and a second side edge, wherein a width of the module substrate is a distance between the first side edge and the second side edge,

wherein the register chip, the first termination resistor and the first plurality of memory chips are arranged in line along the first side edge of the module substrate, and

wherein the second plurality of memory chips are arranged in line along the second side edge of the module substrate.

12. The memory module of claim 11 , wherein the second plurality of memory chips includes:

a fourth memory chip; and

a group of fifth memory chips arranged between the fourth memory chip and the register chip, and

wherein the second termination resistor is arranged between the second side edge and the fourth memory chip.

13. The memory chip of claim 12 , further comprising a plurality of external terminals provided on the module substrate between the second termination resistor and the second side edge.

14. The memory chip of claim 12 , wherein the module substrate further includes a third side edge intersecting each of the first side edge and the second side edge,

wherein the first memory chip and the fourth memory chip are arranged along the third side edge.

15. A memory module comprising:

a module substrate;

a line pattern provided on the module substrate, the line pattern including:

a first branching point;

a second branching point; and

a third branching point;

a first partial line pattern extending from the first branching point to the second branching point, wherein the first partial line pattern includes:

a fourth branching point; and

a fifth branching point between the fourth branching point and the first branching point, wherein the fourth branching point is being between the second branching point and the fifth branching point; and

a second partial hue pattern extending from the first branching point to the third branching point, the second partial line pattern including:

a sixth branching point; and

a seventh branching point between the sixth branching point and the first branching point, wherein the sixth branching point is being between the third branching point and the seventh branching point;

a first memory chip mounted on the module substrate and coupled to the second branching point;

a second memory chip mourned on the module substrate and coupled to the fifth branching point;

a first termination resistor mounted on the module substrate between the first memory chip and the second memory chip and coupled to the fourth branching point;

a second termination resistor mounted on the module substrate and coupled to the third branching point;

a third memory chip mounted on the module substrate and coupled to the sixth branching point; and

a fourth memory chip mounted on the module substrate and coupled to the seventh branching point.

16. The memory module of claim 15 , further comprising a register chip mounted on the module substrate and coupled to the first branching point.

17. The memory module of claim 16 , wherein the first memory chip, the first termination resistor, the second memory chip and the register chip are aligned along a first line, and the third memory chip and the fourth memory chip are aligned along a second line substantially parallel to the first line.

18. The memory module of claim 15 ,

wherein the first partial line pattern further includes at least one eighth branching point between the fifth branching point and the first branching point,

wherein the second partial line pattern further includes at least one ninth branching point between the seventh branching point and the first branching point, and

wherein the memory module further comprises:

at least one fifth memory chip mounted on the module substrate and coupled to the at least one eighth branching point; and

at least one sixth memory chip mounted on the module substrate and coupled to the at least one ninth branching point.

19. The memory module of claim 15 ,

wherein the module substrate includes:

a first side edge;

a second side edge parallel to the first side edge; and

a third side edge intersecting the first side edge to form a first corner, the third side edge further intersecting the second side edge to form a second corner,

wherein the first memory chip is closer to the first corner than the second corner, and

wherein the sixth memory chip is closer to the second corner than the first corner.

20. The memory module of claim 19 , wherein the second termination resistor is arranged between the sixth memory chip and the second side edge.

21. The memory module of claim 20 , further comprising a plurality of external terminals mounted on the module substrate along the second side edge, the plurality of external terminals being arranged between the second termination resistor and the second side edge.