Memory device with dynamic program-verify voltage calibration
A memory system includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for the memory cells, determine a feedback measure based on implementing a processing level for processing data, and dynamically generate an updated target based on adjusting the program-verify target according to the feedback measure.
1. A memory device, comprising:
a memory array including a plurality of memory cells arranged in memory pages; and
a controller coupled to the memory array, the controller configured to:
determine a target profile including edge targets and middle targets, wherein each of the targets represent a program-verify target corresponding to a logic value for the memory cells,
determine a feedback measure based on errors corresponding to a read-level voltage, and
dynamically generate one or more updated targets based on changing one or more of the middle targets according to the feedback measure, wherein the updated target is generated by shifting the corresponding program-verify target by target adjustment values, wherein the target adjustment values are a complementary set of values with a zero sum.
2. The memory device of claim 1 wherein the controller is further configured to determine the feedback measure including an error-difference measure calculated based on error counts corresponding to the read-level voltage and a different read-level voltage.
3. The memory device of claim 2 wherein the error-difference measure is calculated based on a difference in a first error count and a second error count, wherein the first error count corresponds to the read-level voltage and the second error count corresponds to the different read-level voltage offset from the read-level voltage.
4. The memory device of claim 1 wherein the controller is further configured to generate the one or more updated targets based on the feedback measure determined after calibrating the read-level voltage for the memory cells.
5. The memory device of claim 1 wherein the controller is further configured to implement a step calibration mechanism based on the one or more updated targets, wherein the step calibration mechanism generates an adjusted step for dynamically adjusting a programming step for programming the memory cells.
6. The memory device of claim 1 wherein the controller is configured to generate the one or more updated targets independently for each word-line group.
7. The memory device of claim 1 wherein the controller is further configured to generate the one or more updated targets balancing error measures and valley depths across page types for the memory cells, wherein each of the error measures corresponds to the read level voltage for a specific value associated with one of the page types, and wherein the valley depths characterize separations between adjacent program-verify targets.
8. The memory device of claim 1 wherein the controller is further configured to:
determine a reference page type representing one of the page types of the memory cells;
determine a second page type; and
for a target processing period, generate the one or more updated targets corresponding to the reference page type, the second page type, or both.
9. The memory device of claim 8 wherein the controller is further configured to:
determine a third page type different than both the reference page type and the second page type; and
for a subsequent processing period, generate further updated targets corresponding to the reference page type, the third page type, or both.
10. The memory device of claim 1 wherein the controller is further configured to:
identify a high performance page with lowest occurrence of the errors among the page types;
identify a low performance page with highest occurrence of the errors among the page types; and
generate the one or more updated targets for changing the middle targets corresponding to the high performance page, the low performance page, or a combination thereof.
11. The memory device of claim 1 wherein the plurality of memory cells are non-volatile.
12. The memory device of claim 1 wherein the controller is further configured to determine the feedback measure based on an error count associated with a read level voltage.
13. The memory device of claim 1 wherein the controller is further configured to generate the updated target based on adjusting separations between adjacent program-verify targets.
14. The memory device of claim 1 wherein the controller is further configured to generate the updated target balancing an error measure across multiple page types for the memory cells.
15. A method of operating a memory device including a controller and a memory array, the method comprising:
determining a target profile including distribution targets, wherein each of the distribution targets represent a program-verify target corresponding to a logic value for memory cells within the memory array;
determining a feedback measure based on implementing a processing level for processing data; and
dynamically generating, using the controller, an updated target based on adjusting the program-verify target according to the feedback measure for balancing an error measure across multiple page types for the memory cells, wherein generating the updated target includes generating the updated target based on a net-zero sum for the target profile wherein amounts of adjustments to the program-verify targets sum to zero.
16. The method of claim 15 , further comprising implementing a step calibration mechanism, wherein the step calibration mechanism generates an adjusted step for dynamically adjusting a programming step for programming the memory cells.
17. The method of claim 15 , further comprising:
calibrating a read-level voltage for the memory cells; and
wherein:
the feedback measure is calibrated during or after the calibration of the read-level voltage.
18. The method of claim 15 , wherein:
the target profile includes edge targets and middle targets, wherein the edge targets are the distribution targets corresponding to a highest voltage level and a lowest voltage level and the middle targets are the distribution targets between the edge targets;
the feedback measure corresponds to errors associated with a read-level voltage; and
generating the updated target includes updating one or more middle targets according to the feedback measure.
19. The method of claim 18 , further comprising determining the feedback measure including an error-difference measure calculated based on a difference in a first error count and a second error count, wherein the first error count corresponds to the read-level voltage and the second error count corresponds to the different read-level voltage offset from the read-level voltage.
20. The method of claim 18 , wherein generating the updated target includes:
determining a reference page type representing one of the page types of the memory cells;
determining a second page type; and
for a target processing period, generating the updated target based on adjusting one or more of the program-verify targets corresponding to the reference page type, the second page type, or both.
21. The method of claim 20 , wherein generating the updated target includes:
determining a third page type different than both the reference page type and the second page type; and
for a subsequent processing period, generating further updated targets corresponding to the reference page type, the third page type, or both.