IP Library Granted Patent US 10,002,874
Granted Patent B2
US 10,002,874 · App. 15/641,071 · Granted Jun 19, 2018

Method of forming conductive material of a buried transistor gate line and method of forming a buried transistor gate line

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Quick Facts
Patent No.
US 10,002,874
App. No.
15/641,071
Granted
Jun 19, 2018
Kind
B2
Abstract

A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a substrate trench. The precursor is reduced with hydrogen to form elemental-form tungsten material over the material within the substrate trench from the precursor.

Claims (34)

1. A method of forming a buried transistor gate line, comprising:

forming a trench within a substrate comprising semiconductor material;

forming gate insulator material along at least some of sidewalls and at least some of a base of the trench;

forming conductive gate material over the gate insulator material, the forming of the conductive gate material comprising:

adhering a precursor comprising tungsten and chlorine over material within the trench;

reducing the precursor with hydrogen to form elemental-form tungsten material over the material within the trench from the precursor; and

iterating said adhering and reducing to overfill remaining volume of the trench; and

after overfilling remaining volume of the trench, removing uppermost portions of the gate insulator material and conductive gate material to recess them within the trench.

2. The method of claim 1 comprising forming the buried transistor gate line to be part of memory integrated circuitry.

3. A method comprising:

forming a trench within a semiconductor substrate;

lining the trench with an insulative material;

after lining the trench, filling the trench completely with elemental-form tungsten material, wherein the filling the trench completely with the elemental-form tungsten material comprises:

adhering a precursor comprising tungsten and chlorine within the trench;

reducing the precursor with hydrogen to form tungsten material from the precursor; and

iterating the adhering and the reducing until the trench is filled completely with the elemental-form tungsten material; and

removing an upper portion of the elemental-form tungsten material to recess the elemental-form tungsten material so that a lower portion of the elemental-form tungsten material is left within the trench.

4. The method of claim 3 , further comprising, after removing an upper portion of the elemental-form tungsten material, depositing dielectric material to refill the trench completely with the lower portion of the elemental-form tungsten material and the dielectric material.

5. The method of claim 3 , further comprising, after filling the trench completely with the elemental-form tungsten material, removing an upper portion of the insulative material while keeping a lower portion of the insulative material intervening between the lower portion of the elemental-form tungsten material and the trench.

6. The method of claim 5 , wherein the removing the upper portion of the elemental-form tungsten material and the removing the upper portion of the insulative material are carried out simultaneously with each other.

7. The method of claim 3 , wherein the semiconductor substrate includes an active region defined by trench isolation material, and wherein the trench is formed to cross over the active region to reach the trench isolation material.

8. A method comprising:

forming a trench in a semiconductor substrate;

lining the trench with dielectric liner material;

providing the semiconductor substrate with the trench to a process chamber;

introducing a precursor gas into the process chamber together with an inert gas to adhere the precursor within the trench, the precursor comprising tungsten and chlorine;

purging the precursor gas from the process chamber;

introducing a reducing gas into process chamber together with the inert gas to reduce the precursor so that elemental-form tungsten material is formed within the trench from the precursor, the reducing gas consisting of a hydrogen gas;

purging the reducing gas from the process chamber;

iterating the introducing the precursor gas, the purging the precursor gas, the introducing the reducing gas and the purging the reducing gas multiple times until the trench is overfilled with the elemental-form tungsten material; and

removing an upper portion of the elemental-form tungsten material to recess the elemental-form tungsten material so that a lower portion of the elemental-form tungsten material is left within the trench.

9. The method of claim 8 , further comprising depositing a second dielectric material to re-overfill the trench with the lower portion of the elemental-form tungsten material and the dielectric material.

10. The method of claim 9 , wherein the process chamber includes a susceptor that is set to a temperature range of about 400° C. to about 500° C., and the semiconductor substrate rests on the susceptor.

11. The method of claim 8 , wherein a pressure range within the process chamber is set to a range of about 10 Torr to about 50 Torr during the introducing the precursor gas and the introducing the reducing gas.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
Cited By (1)
US 12,604,458