Self-boost, source following, and sample-and-hold for accessing memory cells
Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.
1. An electronic memory apparatus, comprising:
a memory cell coupled between a first access line and a second access line;
a capacitor, separate from the memory cell, coupled between the first access line and a first voltage source;
a second voltage source coupled with the first access line via a first switching component; and
a sensing component coupled with the first access line at a first terminal of the sensing component and coupled with a reference voltage source at a second terminal of the sensing component, the sensing component configured to detect a logic state stored by the memory cell based at least in part on a flow of charge between the capacitor and the first access line.
2. The electronic memory apparatus of claim 1 , further comprising:
an amplifier coupled between the capacitor and the sensing component.
3. The electronic memory apparatus of claim 2 , wherein the amplifier is coupled with the second voltage source via a second switching component.
4. The electronic memory apparatus of claim 1 , further comprising:
a reference line coupled between the reference voltage source and the sensing component; and
another capacitor, separate from the memory cell, coupled between the reference line and the first voltage source,
wherein the sensing component is configured to detect the logic state stored by the memory cell based at least in part on a flow of charge between the other capacitor and the reference line.
5. The electronic memory apparatus of claim 4 , wherein the reference voltage source is coupled with the reference line via a third switching component.
6. The electronic memory apparatus of claim 4 , further comprising:
an amplifier coupled between the capacitor and the sensing component
another amplifier coupled between the other capacitor and the sensing component.
7. The electronic memory apparatus of claim 6 , wherein:
the amplifier is coupled with the second voltage source via a second switching component; and
the other amplifier is coupled with the second voltage source via a fourth switching component.
8. The electronic memory apparatus of claim 1 , wherein the second terminal of the sensing component is coupled with the first access line, and the electronic memory apparatus comprises:
a first isolation component coupled between the first terminal of the sensing component and the first access line, the first isolation component operable to, after generating a first sense voltage at the first terminal of the sensing component, isolate the first terminal of the sensing component from the first access line during a generation of a reference voltage on the first access line.
9. The electronic memory apparatus of claim 8 , further comprising:
a second isolation component coupled between the second terminal of the sensing component and the first access line.
10. A method, comprising:
applying a first voltage to a first terminal of a capacitor, separate from a memory cell, that is coupled with a first access line of the memory cell;
applying a second voltage to a second terminal of the capacitor;
applying a third voltage to the second terminal of the capacitor before selecting the memory cell for a sensing operation;
selecting the memory cell for the sensing operation;
comparing a resultant voltage of first access line to a reference voltage at the sensing component, wherein the resultant voltage is based at least in part on selecting the memory cell for the sensing operation and on a flow of charge between the capacitor and the first access line that is based at least in part on applying the first voltage and the third voltage to the capacitor; and
determining a logic value associated with the memory cell based at least in part on comparing the resultant voltage and the reference voltage at the sensing component.
11. The method of claim 10 , wherein applying the first voltage to the first terminal of the capacitor comprises:
activating a switching component coupled between the first terminal of the capacitor and a first voltage source.
12. The method of claim 11 , further comprising:
deactivating the switching component coupled between the first terminal of the capacitor and the first voltage source prior to applying the third voltage to the second terminal of the capacitor.
13. The method of claim 11 , wherein applying the third voltage to the second terminal of the capacitor comprises:
activating a switching component coupled between the second terminal of the capacitor and the first voltage source.
14. The method of claim 10 , further comprising:
applying the second voltage to the second terminal of the capacitor after selecting the memory cell for the sensing operation.
15. The method of claim 10 , further comprising:
applying the second voltage and the third voltage to a terminal of another capacitor, separate from the memory cell, that is coupled with the sensing component, wherein the reference voltage is based at least in part on applying the second voltage and the third voltage to the terminal of the other capacitor.
16. The method of claim 15 , further comprising:
applying a fourth voltage to another terminal of the other capacitor, wherein the reference voltage is based at least in part on applying the fourth voltage to the other terminal of the other capacitor.
17. The method of claim 15 , further comprising:
enabling a first amplifier on the first access line that is coupled between the memory cell and the sense component, wherein the resultant voltage of first access line is based at least in part on enabling the first amplifier; and
enabling a second amplifier that is coupled between a reference voltage source and the sense component wherein the reference voltage is based at least in part on enabling the second amplifier.
18. The method of claim 10 , further comprising:
enabling an amplifier coupled between the memory cell and the sense component on the first access line, wherein the resultant voltage of first access line is based at least in part on enabling the amplifier.
19. The method of claim 18 , wherein enabling the amplifier coupled between the first access line and the sense component comprises:
activating a switching component coupled between the amplifier and a voltage source.
20. The method of claim 18 , further comprising:
isolating a first terminal of the sense component from the first access line before the comparing to hold the resultant voltage at the first terminal of the sense component while the reference voltage is generated.
21. The method of claim 20 , further comprising:
applying, after isolating the first terminal of the sense component, the first voltage to the first terminal of the capacitor and the second voltage to the second terminal of the capacitor;
applying the third voltage to the second terminal of the capacitor before selecting the memory cell for a second selection operation;
selecting the memory cell for the second sensing operation; and
enabling the amplifier for a second time, wherein the reference voltage is based at least in part on selecting the memory cell for the second sensing operation and enabling the amplifier for the second time.
22. The method of claim 10 , further comprising:
isolating a first terminal of the sense component from the first access line before the comparing to hold the resultant voltage at the first terminal of the sense component while the reference voltage is generated.
23. The method of claim 22 , further comprising:
applying, after isolating the first terminal of the sense component, the first voltage to the first terminal of the capacitor and the second voltage to the second terminal of the capacitor;
applying the third voltage to the second terminal of the capacitor before selecting the memory cell for a second selection operation; and
applying the selection voltage to the second access line of the memory cell to select the memory cell for the second sensing operation, wherein the reference voltage is based at least in part on selecting the memory cell for the second sensing operation.
24. The electronic memory apparatus of claim 9 , further comprising:
an amplifier coupled between the capacitor and both the first isolation component and the second isolation component.
25. The electronic memory apparatus of claim 24 , wherein the amplifier is coupled with the second voltage source via a second switching component.