IP Library Granted Patent US 10,147,475
Granted Patent B1
US 10,147,475 · App. 15/590,143 · Granted Dec 4, 2018

Refresh in memory based on a set margin

Inventors: Marco Sforzin (Cernusco Sul Naviglio, IT); Paolo Amato (Treviglio, IT)
Assignee: Micron Technology, Inc.
G11C11/406G05F3/26G11C11/40607G11C16/0483G11C16/10G11C16/349G11C2207/104G11C2211/4062
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Quick Facts
Patent No.
US 10,147,475
App. No.
15/590,143
Filed
May 9, 2017
Granted
Dec 4, 2018
Kind
B1
Art Unit
2825
USPC
365/185.22
Abstract

The present disclosure includes apparatuses and methods related to refresh in memory. An apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage. The reference voltage can be determined by the threshold voltage being within a set margin of a second state.

Claims (9)

1. A method, comprising:

measuring a voltage associated with a first number of memory cells in an array of memory cells; and

refreshing the array of memory cells in response to the voltage being within a set margin of a reference voltage, wherein the set margin is based on an amount of time to complete refreshing the array of memory cells and the set margin is based on the speed and size of a memory device to have enough time to do a refresh operation before reaching the reference voltage, and wherein the memory device includes the array of memory cells and a monitor array.

2. The method of claim 1 , wherein refreshing the array of memory cells improves read margin of the array of memory cells.

3. An Apparatus, comprising:

an array of memory cells; and

a controller configured to:

measure a voltage associated with a first number of memory cells in the array of memory cells; and

refresh the array of memory cells in response to the voltage being within a set margin of a reference voltage, wherein the set margin is based on an amount of time to complete the refresh of the array of memory cells and the set margin is based on the speed and size of a memory device to have enough time to do a refresh operation before reaching the reference voltage, and wherein the memory device includes the array of memory cells and a monitor array.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2017
From: SFORZIN, MARCO; AMATO, PAOLO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042426/0482 →