Memory cells having an access gate and a control gate and dielectric stacks above and below the access gate
View Patent ↗In an example, a memory cell may have an access gate, a control gate coupled to the access gate, a first dielectric stack below an upper surface of a semiconductor, above the access gate, and between a first portion of the control gate and the semiconductor, and a second dielectric stack below the access gate and the first dielectric stack and between a second portion of the control gate and the semiconductor. Each of the first and second dielectric stacks may store a charge.
1. A memory cell, comprising:
an access gate;
a control gate coupled to the access gate;
a first dielectric stack below an upper surface of a semiconductor, above the access gate, and between a first portion of the control gate and the semiconductor; and
a second dielectric stack below the access gate and the first dielectric stack and between a second portion of the control gate and the semiconductor;
wherein each of the first and second dielectric stacks is to store a charge;
wherein the first dielectric stack and the second dielectric stack each comprise an interface dielectric lateral to the semiconductor, a tunnel dielectric lateral to the interface dielectric, a charge trap lateral to the tunnel dielectric, and a blocking dielectric lateral to the charge trap, and further comprising an interface metallic lateral to the blocking dielectric of each of the first dielectric stack and the second dielectric stack, wherein the first portion of the control gate is lateral to the interface metallic lateral to the blocking dielectric of the first dielectric stack and the second portion of the control gate is lateral to the interface metallic lateral to the blocking dielectric of the second dielectric stack; and
wherein a first storage dielectric is laterally between the interface dielectric and the tunnel dielectric and a second storage dielectric is laterally between the charge trap and the blocking dielectric.
2. The memory cell of claim 1 , further comprising an additional dielectric between the semiconductor and the access gate and between the first dielectric stack and the second dielectric stack.
3. The memory cell of claim 1 , wherein the control gate is a single continuous structure.
4. The memory cell of claim 1 , further comprising a first source/drain in the semiconductor and adjacent to the first dielectric stack and a second source/drain in the semiconductor and adjacent to the second dielectric stack.
5. The memory cell of claim 4 , wherein the first source/drain is above the second source/drain.
6. The memory cell of claim 5 , wherein an upper surface of the first source/drain is coplanar with the upper surface of the semiconductor.
7. The memory cell of claim 1 , wherein the memory cell is a USUM memory cell.
8. The memory cell of claim 1 , wherein the first dielectric stack and the second dielectric stack each further comprise a first storage dielectric between the interface dielectric and the tunnel dielectric and a second storage dielectric between the charge trap and the blocking dielectric.
9. The memory cell of claim 1 , wherein the interface dielectric comprises OR—SiON, the first storage dielectric comprises i-SRN, the tunnel dielectric comprises HfSiON, the charge trap comprises GaN, the second storage dielectric comprises i-SRN, and the blocking dielectric comprises HfSiON or HfSiON and AL 2 O 3 .
10. A memory cell, comprising:
a first source/drain;
a second source/drain below an upper surface of a semiconductor and below the first source/drain;
a channel in the semiconductor between the first source/drain and the second source/drain;
a first non-volatile portion lateral to the channel and adjacent to the first source/drain;
a second non-volatile portion lateral to the channel, below the first non-volatile portion, and adjacent to the second source/drain; and
a gate between the first non-volatile portion and the second non-volatile portion and lateral to the channel;
wherein the gate is an access gate that is coupled to a control gate, and wherein the first non-volatile portion comprises a first dielectric stack and a first portion of the control gate coupled to the first dielectric stack and the second non-volatile portion comprises a second dielectric stack and a second portion of the control gate coupled to the second dielectric stack; and
wherein the first and second dielectric stacks each comprise an interface dielectric lateral to the channel, a first storage dielectric lateral to the interface dielectric, a tunnel dielectric lateral to the first storage dielectric, a charge trap lateral to the tunnel dielectric, a second storage dielectric lateral to the charge trap, and a blocking dielectric lateral to the second storage dielectric, wherein the first portion of the control gate is lateral to the blocking dielectric for the first dielectric stack and the second portion of the control gate is lateral to the blocking dielectric for the second dielectric stack.
11. The memory cell of claim 10 , wherein the channel is to couple the first non-volatile portion and the second non-volatile portion in series between the first source/drain and the second source/drain.
12. The memory cell of claim 11 , further comprising a fixed-threshold-voltage portion between the first non-volatile portion and the second non-volatile portion and that comprises the access gate, wherein the channel is to couple the fixed-threshold-voltage portion in series with the first non-volatile portion and the second non-volatile portion.
13. A memory array, comprising:
a first memory cell and a second memory cell in a region that extends below an upper surface of a semiconductor;
wherein the first memory cell and the second memory cell are respectively adjacent to respective portions of the semiconductor that respectively form sides of the region;
wherein each of the first and second memory cells comprises:
a control gate;
a first dielectric stack between a first portion of the control gate and the respective portion of the semiconductor, the first dielectric stack to store a charge;
a second dielectric stack below the first dielectric stack and between a second portion of the control gate and the respective portion of the semiconductor, the second dielectric stack to store a charge; and
an access gate coupled to the control gate and between the first dielectric stack and the second dielectric stack;
wherein the control gate is below the upper surface of the semiconductor and is coupled to a program line that is below the upper surface of the semiconductor, and wherein the access gate is below the upper surface of the semiconductor and is coupled to an access line that is below the upper surface of the semiconductor.
14. The memory array of claim 13 , wherein the respective portion of the semiconductor to which the first memory cell is adjacent comprises a first source/drain of the first memory cell adjacent to the first dielectric stack of the first memory cell, wherein the respective portion of the semiconductor to which the second memory cell is adjacent comprises a first source/drain of the second memory cell adjacent to the first dielectric stack of the second memory cell, and further comprising a second source/drain common to the first and second memory cells and below the first source/drain of the first memory cell and below the first source/drain of the second memory cell.
15. The memory array of claim 14 , wherein a first portion of the second source/drain forms a bottom of the region that extends below the upper surface of the semiconductor, wherein a second portion of the second source/drain extends into the respective portion of the semiconductor to which the first memory cell is adjacent and is adjacent to the second dielectric stack of the first memory cell, and wherein a third portion of the second source/drain extends into the respective portion of the semiconductor to which the second memory cell is adjacent and is adjacent to the second dielectric stack of the second memory cell.
16. The memory array of claim 14 , wherein an upper surface of the first source/drain of the first memory cell and an upper surface of the first source/drain of the second memory cell are coplanar with the upper surface of the semiconductor, and wherein a data line is above the upper surface of the semiconductor and is coupled to the upper surface of the first source/drain of the first memory cell and to the upper surface of the first source/drain of the second memory cell.
17. The memory array of claim 14 , further comprising a conductor laterally between the first and second memory cells in the region that extends below the upper surface of the semiconductor, wherein the conductor is coupled to the second source/drain, and wherein the conductor is below the upper surface of the semiconductor and is connected to a contact outside of the memory array.
18. A memory array, comprising:
a first memory cell and a second memory cell in a region that extends below an upper surface of a semiconductor;
wherein the first memory cell and the second memory cell are respectively adjacent to respective portions of the semiconductor, wherein the respective portions of the semiconductor respectively comprise respective sidewalls that respectively form sides of the region;
a control gate;
a first dielectric stack between a first portion of the control gate and the respective portion of the semiconductor, the first dielectric stack to store a charge;
a second dielectric stack below the first dielectric stack and between a second portion of the control gate and the respective portion of the semiconductor, the second dielectric stack to store a charge; and
an access gate coupled to the control gate and between the first dielectric stack and the second dielectric stack;
wherein the respective portion of the semiconductor to which the first memory cell is adjacent comprises a first source/drain of the first memory cell adjacent to the first dielectric stack of the first memory cell, wherein the respective portion of the semiconductor to which the second memory cell is adjacent comprises a first source/drain of the second memory cell adjacent to the first dielectric stack of the second memory cell, and further comprising a second source/drain common to the first and second memory cells and below the first source/drain of the first memory cell and below the first source/drain of the second memory cell; and
a conductor laterally between the first and second memory cells in the region that extends below the upper surface of the semiconductor, wherein the conductor is coupled to the second source/drain, and wherein the conductor is below the upper surface of the semiconductor and is connected to a contact outside of the memory array.