Apparatuses including test segment circuits having latch circuits for testing a semiconductor die

1. An apparatus, comprising:

a plurality of segment lines configured to form a ring around a die, each segment line comprising:

a portion of a first signal line;

a portion of a second signal line; and

a portion of a third signal line; and

a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines,

each test segment circuit coupled to the portion of the first signal line, the portion of the second signal line, and the portion of the third signal line, and

each test segment circuit configured to control an operation performed on at least one segment line of the plurality of segment lines, wherein each test segment circuit comprises:

a respective first latch circuit configured to receive a first signal that activates the respective test segment circuit and configured to receive a second signal that clocks the respective test segment circuit; and

a respective second latch circuit configured to receive a third signal from the first latch circuit and configured to transmit a fourth signal that activates an adjacent test segment circuit.

2. The apparatus of claim 1 , wherein the respective first latch circuit further configured to receive a fifth signal that enables testing of each segment line of the plurality of segment lines, and wherein the respective second latch circuit further configured to receive an inverted version of the fifth signal.

3. The apparatus of claim 2 , wherein each test segment circuit coupled to the respective portion of the third signal line via a coupling to the respective first latch circuit and a coupling to a first inverter configured to receive an inverted fifth signal that activates the second latch circuit.

4. The apparatus of claim 1 , wherein each test segment circuit comprises:

a transistor configured to receive, at a first node of the transistor, the third signal, the third signal received from the first latch circuit; and

a switch, coupled to the transistor, configured to receive a sixth signal that activates the switch, the sixth signal received from the first latch circuit.

5. The apparatus of claim 4 , wherein each test segment circuit coupled to the respective portion of the second signal line via a coupling to the transistor and a coupling to the switch.

6. The apparatus of claim 5 , wherein the respective portion of the second signal line is configured to supply the transistor when the third signal activates a pull-down mode of the transistor.

7. The apparatus of claim 5 , wherein the switch is configured to decouple preceding segment lines relative to respective segment line, when the third signal activates the pull-down mode of the transistor, to the subsequent segment lines of the respective segment line.

8. The apparatus of claim 7 , wherein, when the third signal activates the pull-down mode of the transistor, a die crack detection circuit configured to test the head or tail of the second signal line for a die crack in the die.

9. The apparatus of claim 1 , wherein each test segment circuit comprises:

a second inverter configured to provide the second signal that clocks the respective test segment circuit;

a NAND gate; and

a third inverter coupled to the NAND gate and configured to receive an output of the NAND gate responsive to an output of the second latch circuit.

10. The apparatus of claim 9 , wherein each test segment circuit is coupled to the respective portion of the first signal line via a coupling to the NAND gate and the third inverter.