Method and apparatus for precharge and refresh control
Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller that transmits a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time. The first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation. The memory device receives the first command and the plurality of address signals and further performs the second memory operation to the first bank responsive, at least a part, to the plurality of address signals and the first command.
1. An apparatus, comprising:
a command decoder configured to receive a first command and a second command, and further configured to provide a first control signal and a second control signal responsive to the first command and the second command, respectively;
an address decoder configured to receive at least a portion of address signals and further configured to activate one bank selection signal of a plurality of bank selection signals corresponding to a plurality of banks, responsive to the at least a portion of address signals; and
a plurality of control logic circuits, wherein each control logic circuit of the plurality of control logic circuits is configured to receive the first control signal, the second control signal and a corresponding bank selection signal of the plurality of bank selection signals,
wherein the first command is indicative of performing a first memory operation for a first bank of the plurality of banks identified by the at least a portion of address signals, and the second command is indicative of performing the first memory operation and a second memory operation different from the first memory operation for the first bank of the plurality of banks, and
wherein a control logic circuit of the plurality of control logic circuits corresponding to the first bank is configured to provide a bank row activation signal to the first bank responsive to the bank selection signal corresponding to the first bank and the second control signal in the second memory operation.
2. The apparatus of claim 1 , wherein the first memory operation is a precharge operation and the second memory operation is a refresh operation.
3. The apparatus of claim 2 , wherein the control logic circuit of the plurality of control logic circuits comprises:
a bank active status circuit configured to provide a bank status flag signal indicative of whether the corresponding bank is in an active state; and
a bank row activation circuit configured to provide the bank row activation signal responsive, at least in part, to the bank status flag signal, and
wherein the bank row activation circuit is configured to provide the bank row activation signal in an active state responsive to the bank status flag signal in an active state, and further configured to provide the bank row activation signal in an inactive state responsive to the bank status flag signal in an inactive state.
4. The apparatus of claim 3 , wherein the control logic circuit of the plurality of control logic circuits comprises a row access cycle timer configured to count a row access cycle time and further configured to provide a time up signal, and
wherein the bank row activation circuit is configured to provide the bank row activation signal in an inactive state responsive, at least in part, to the time up signal.
5. The apparatus of claim 4 , wherein the control logic circuit of the plurality of control logic circuits further comprises a precharge timer configured to count a precharge time and further configured to provide a precharge time up signal after counting the precharge time responsive, at least in part, to the bank status flag signal and the bank selection signal, and
wherein the row access cycle timer is configured to count the row access cycle time, at least in part, to the precharge time up signal.
6. The apparatus of claim 5 , wherein the precharge timer is configured to disable counting the precharge time responsive, at least in part, to the bank status flag signal in an inactive state.
7. The apparatus of claim 6 , wherein at least one of the refresh timer and the precharge timer is a digital countdown-counter.
8. The apparatus of claim 6 , wherein at least one of the refresh timer and the precharge timer is a programmable counter.
9. The apparatus of claim 6 , wherein at least one of the refresh timer and the precharge timer is an analog timer.
10. The apparatus of claim 1 , wherein the plurality of control logic circuits are configured to determine whether the first bank is in the active state responsive to the first command, and further configured to perform the first memory operation before performing the second memory operation for the first bank if the first bank is in the active state.
11. The apparatus of claim 10 , wherein the plurality of control logic circuits is further configured to perform the first memory operation before second memory operation to the first bank responsive to the first command, and
wherein the memory device is configured to perform the second memory operation responsive to the second command.