Granted Patent B2

US 12,693,965 · App. 18/774,730 · Granted Jul 28, 2026

Inventor: Randall J. Rooney (Boise, ID)

Assignee: Micron Technology, Inc.

G06F12/02G06F2212/1041

Abstract

Claims (46)

1 . An apparatus comprising:

an aggressor address queue configured to store aggressor addresses;

a sequential refresh address generator circuit configured to generate a refresh address based on sequence logic responsive to a refresh command;

a targeted refresh address generator configured to generate the refresh address based on an aggressor address of the aggressor addresses stored in the aggressor address queue responsive to a refresh management command; and

a self-refresh logic circuit configured to check a state of the aggressor address queue and generate a mix of at least one refresh signal and at least one targeted refresh signal until the aggressor address queue is empty during a self-refresh mode,

wherein the refresh command and the refresh management command are provided together by a controller coupled to the apparatus,

wherein the sequential refresh address generator circuit is configured to generate the refresh address based on the sequence logic responsive to the at least one refresh signal, and

wherein the targeted refresh address generator is configured to generate the refresh address based on the aggressor address of the aggressor addresses stored in the aggressor address queue responsive to the at least one targeted refresh signal.

2 . The apparatus of claim 1 , wherein the targeted refresh address generator does not generate the refresh address responsive to the refresh command and the sequential refresh address generator circuit does not generate the refresh address responsive to the refresh management command.

3 . The apparatus of claim 1 , further comprising:

a memory array; and

a row decoder,

wherein the row decoder is configured to refresh one or more word lines of the memory array associated with the refresh address.

4 . The apparatus of claim 1 , further comprising an aggressor detector circuit configured to identify the aggressor address.

5 . The apparatus of claim 4 , further comprising:

a memory array including a plurality of word lines, each of which is configured to store a count value associated with the word line, wherein the aggressor detector circuit is configured to identify the aggressor address based on the count value.

6 . A system comprising:

a controller configured to provide a refresh command and a refresh management command together; and

a memory coupled to the controller and configured to perform a sequential refresh operation but not a targeted refresh operation responsive to the refresh command and configured to perform the targeted refresh operation but not the sequential refresh operation responsive to the refresh management command,

wherein the memory is further configured to perform a mix of at least one sequential refresh operation and at least one targeted refresh operation responsive to the refresh command and the refresh management command being provided together.

7 . The system of claim 6 , wherein the memory includes a plurality of banks and wherein responsive to the refresh management command the memory performs the targeted refresh operation on a selected one of the plurality of banks.

8 . The system of claim 6 , wherein the controller comprises a counter circuit which stores a plurality of count values, each associated with one of a plurality of banks of the memory, and

wherein responsive to providing the refresh management command but not responsive to providing the refresh command, one of the plurality of count values is changed.

9 . The system of claim 8 , wherein responsive to the controller providing an access command the counter circuit changes one of the plurality of count values.

10 . The system of claim 6 , wherein the memory includes a refresh address generator with a sequential refresh address generator circuit and a targeted refresh address generator circuit,

wherein responsive to the refresh command the sequential refresh generator circuit but not the targeted refresh address generator circuit provides a refresh address, and

wherein responsive to the refresh management command the targeted refresh address generator circuit but not the sequential refresh address generator circuit provides the refresh address.

11 . The system of claim 6 , wherein the memory includes an aggressor detector circuit configured to identify an aggressor address, wherein the targeted refresh address generator circuit is configured to generate the refresh address based on the aggressor address.

12 . The system of claim 6 , wherein the controller is configured to enter the memory into a self-refresh mode, and wherein the memory is configured to perform sequential refresh operations during the self-refresh mode.

13 . A method comprising:

receiving, from a controller, a first type of refresh command and a second type of refresh command together at a memory; and

performing a mix of a first type of refresh operations and a second type of refresh operations responsive to receiving the first type of refresh command and the second type of refresh command together.

14 . The method of claim 13 , further comprising:

performing the first type of refresh operation but not the second type of refresh operation responsive to the first type of refresh command; and

performing the second type of refresh operation but not the first type of refresh operation responsive to the second type of refresh command.

15 . The method of claim 13 , wherein the first type of refresh command is a refresh command and the first type of refresh operation is a sequential refresh operation, and wherein the second type of refresh command is a refresh management command and the second type of refresh operation is a targeted refresh operation.

16 . The method of claim 13 , further comprising:

identifying an aggressor address and storing the aggressor address in an aggressor queue; and

generating a refresh address based on the aggressor address in the aggressor queue responsive to the second type of refresh command.

17 . The method of claim 13 , further comprising generating the refresh address responsive to the first type of refresh command based on a previous refresh address generated responsive to the first type of refresh command.

18 . The method of claim 13 , further comprising:

providing access commands to a bank of the memory:

changing a count value in a first direction responsive to providing the access commands;

providing the second type of refresh command responsive to the count value crossing a threshold; and

changing the count value in a second direction responsive to providing the second type of refresh.

19 . The method of claim 18 , further comprising periodically providing the first type of refresh command and not changing the count value responsive to the first type of refresh command.

Assignments (1)

Continuity (2)

References Cited (400)