Post package repairing method, method of preventing multiple activation of spare word lines, and semiconductor memory device including fuse programming circuit
Provided is a method of preventing simultaneous activation of redundancy memory line or spare word lines, the method including: programming a fail address of a memory line determined to be defective; reprogramming the fail address if a first spare line for the memory line is determined to be defective; storing additional information with respect to the reprogrammed fail address; and activating a second spare line and inactivating the first spare line, referring to the additional information.
1. A method of managing spare lines, comprising:
programming a fail address of a word line determined to be defective;
reprogramming the fail address if a first spare line for the word line is determined to be defective;
storing additional information with respect to the reprogrammed fail address; and
activating a second spare line and inactivating the first spare line, referring to the additional information
wherein the storing comprises programming an additional bit for the programmed fail address,
wherein the second spare line is activated referring to the additional bit, and
wherein the additional bit is programmed based on history information about a previous repair of a memory cell connected to the word line.
2. The method of claim 1 , wherein the first or second spare line is a spare word line among the spare word line and a spare bit line.
3. The method of claim 1 , further comprising generating a priority signal and a blocking signal,
wherein the second spare line is activated by the priority signal and all other spare lines including the first spare line are inactivated by the blocking signal.
4. The method of claim 1 , wherein if the second spare line is determined to be defective, information indicating a further repair of the memory cell is impossible is output.
5. The method of claim 1 , wherein the fail address is programmed and reprogrammed using an anti-fuse array unit of an anti-fuse circuit comprising a plurality of anti-fuse array units, the anti-fuse array unit including at least one anti-fuse.
6. The method of claim 1 , wherein the additional information is stored regardless of history information about a previous repair of a memory cell connected to the word line.
7. The method of claim 1 , wherein the additional information is indicated at an anti-fuse array unit of an anti-fuse circuit comprising a plurality of anti-fuse array units, the anti-fuse array unit including at least one anti-fuse and being used for the reprogramming the fail address.
8. The method of claim 1 , wherein a memory cell connected with the spare line is a dynamic random access memory (DRAM) cell.
9. The method of claim 1 , wherein the additional information is stored in a form of at least one or more bits.
10. The method of claim 1 , wherein the additional information is indicated at an anti-fuse array unit of an anti-fuse circuit comprising a plurality of anti-fuse array units, the anti-fuse array unit including at least one anti-fuse and being used for the programming the fail address.
11. The method of claim 1 , wherein the additional bit is programmed by rupturing an anti-fuse of an anti-fuse array comprising a plurality of anti-fuse arrays, the anti-fuse array being used for the programming the fail address.
12. The method of claim 1 , wherein a memory cell connected with the first or second spare line is a volatile memory cell.
13. The method of claim 1 , further comprising programming an additional bit for the reprogrammed fail address if the second spare line is determined to be defective.
14. A semiconductor memory device, comprising:
a circuitry configured to program a fail address of a word line determined to be defective, reprogram the fail address if a first spare line for the word line is determined to be defective, and store additional information with respect to the reprogrammed fail address;
a memory cell array including a normal memory cell block, including the word line, and a spare cell block including the first spare line; and
a control circuit configured to activate a second spare line in the spare cell block and inactivate the first spare line, referring to the additional information,
wherein the circuitry programs an additional bit for the programmed fail address,
wherein the second spare line is activated referring to the additional bit, and
wherein the additional bit is programmed based on history information about a previous repair of a memory cell connected to the word line.