Semiconductor memory device for controlling operation of delay-locked loop circuit
A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.
1. A semiconductor memory device, comprising:
a delay-locked loop circuit that receives an external clock signal and that performs a locking operation on the external clock signal and on an internal clock signal output from the delay-locked loop circuit to obtain a locked state; and
a control unit that controls the delay-locked loop circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks, the auto-refresh period comprising both the updating period and a noise period.
2. The semiconductor memory device of claim 1 , wherein the noise period of the auto-refresh period comprises a period in which a power voltage or a ground voltage varies.
3. The semiconductor memory device of claim 1 , wherein the updating period of the auto-refresh period comprises a period in which all of the memory banks do not perform the auto-refresh operation.
4. The semiconductor memory device of claim 1 , wherein the control unit, in response to an auto-refresh request signal that indicates the auto-refresh period and an auto-refresh end signal that indicates that the noise period has ended, outputs a control signal to the delay-locked loop circuit to control a locking operation of the delay-locked loop circuit.
5. The semiconductor memory device of claim 4 , wherein the control unit comprises an AND gate that performs a logical AND operation on the auto-refresh request signal and the auto-refresh end signal and outputs the control signal as a result of the logical AND operation.
6. The semiconductor memory device of claim 4 , wherein:
the memory banks are grouped into memory bank groups;
the control unit comprises an AND gate that performs a logical AND operation; and
when the semiconductor memory device performs the auto-refresh operation on each of the memory bank groups, the AND gate performs a logical AND operation on memory bank group end signals for respectively indicating that the memory banks in each of the memory bank groups have ended the auto-refresh operation and to output the auto-refresh end signal.
7. A semiconductor memory device, comprising:
a delay-locked loop circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal output from the delay-locked loop circuit to obtain a locked state; and
a control unit that controls the delay-locked loop circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks, the auto-refresh period comprising both the updating period and a noise period,
wherein the auto-refresh operation is performed in the noise period.
8. The semiconductor memory device of claim 7 , wherein the updating period of the auto-refresh period constitutes a period in which all of the memory banks do not perform the auto-refresh operation.
9. The semiconductor memory device of claim 7 , wherein the control unit in response to an auto-refresh request signal that indicates the auto-refresh period and an auto-refresh end signal that indicates that the noise period has ended, outputs a control signal to the delay-locked loop circuit to control a locking operation of the delay-locked loop circuit.
10. The semiconductor memory device of claim 9 , wherein the control unit comprises an AND gate performing a logical AND operation on the auto-refresh request signal and the auto-refresh end signal, thereby outputting the control signal.
11. The semiconductor memory device of claim 9 , wherein:
the memory banks are grouped into memory bank groups;
the control unit comprises an AND gate that performs a logical AND operation; and
when the semiconductor memory device performs the auto-refresh operation on each of the memory bank groups, the AND gate performs a logical AND operation on memory bank group end signals for respectively indicating that the memory banks in each of the memory bank groups have ended the auto-refresh operation and to output the auto-refresh end signal.
12. A method of operating a delay-locked loop during an auto-refresh period of an auto-refresh operation that refreshes memory banks, the auto-refresh period having a noise period and an updating period, the method comprising:
determining the updating period where an auto-refresh request is enabled and an auto-refresh ends;
generating a delay-locked loop control signal during the updating period; and
applying the delay-locked loop control signal to the delay-locked loop during the updating period to maintain a locked state of a locking operation of the delay-locked loop.
13. The method of claim 12 , further comprising:
grouping the memory banks into memory bank groups; and
when the auto-refresh operation is performed on each of the memory bank groups, performing a logical AND operation on memory bank group end signals for respectively indicating that the memory banks in each of the memory bank groups have ended the auto-refresh operation, and to provide an indication that the auto-refresh ends.