Memory refresh methods, memory section control circuits, and apparatuses
Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
1. An apparatus, comprising:
a plurality of memory sections; and
a plurality of memory section control circuits, wherein each memory section control circuit is coupled to a respective one of the plurality of memory sections, wherein each memory section control circuit comprises a plurality of access line drivers, and wherein each of the access line drivers comprises a plurality of transistors having commonly coupled gates,
wherein, during an operation of the apparatus in which a memory section of the plurality of memory sections is active and a memory section of the plurality of memory sections is inactive, a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to the active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to the inactive memory section control circuit, wherein the first voltage is greater than the second voltage
wherein each of the memory section control circuits comprises a plurality of global drivers configured to receive either the first voltage or the second voltage.
2. The apparatus of claim 1 , further comprising:
a self-refresh controller coupled to the plurality of memory section control circuits and configured to provide a row address.
3. The apparatus of claim 1 , wherein the first voltage is provided responsive to receipt of an inactive enable signal.
4. The apparatus of claim 1 , wherein during an operation of the apparatus in which a memory section of the plurality of memory sections is active and a memory section of the plurality of memory sections is inactive, a third voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to the active memory section, wherein the third voltage is lower than the second voltage.
5. The apparatus of claim 4 , wherein the third voltage is provided responsive to receipt of an active enable signal.
6. The apparatus of claim 1 , further comprising:
a plurality of access lines coupled to the at least some of the access line drivers of the memory section control circuit coupled to the active memory section, wherein the access lines are configured to deactivate responsive to the memory section control circuit providing the first voltage.
7. The apparatus of claim 1 wherein each of the access line drivers comprise:
a p-channel field effect transistor; and
an n-channel field effect transistor.
8. The apparatus of claim 1 wherein each of the memory section control circuits further comprises a pre-decoder configured to receive an undecoded row address and to provide a pre-decoded row address to the global drivers of that memory section control circuit.
9. A memory section control circuit, comprising:
a plurality of access line drivers;
a decoder voltage supply configured to provide a first voltage responsive to selection of a memory section corresponding to the memory section control circuit, and to otherwise provide a second voltage, wherein the first voltage is greater than the second voltage; and
a decoder comprising a plurality of global drivers, wherein each of the drivers is configured to receive the voltage provided by the decoder voltage supply, wherein each of the global drivers is configured to provide a third voltage to a respective section of the plurality of access line drivers responsive to decoding a row address corresponding to an access line coupled to an access line driver of the respective section, and to otherwise provide the voltage provided by the decoder voltage supply.
10. The memory section control circuit of claim 9 , wherein the first voltage comprises a pumped supply voltage and the second voltage comprises a common supply voltage.
11. The memory section control circuit of claim 9 , wherein each of access line drivers is configured to deactivate a corresponding access line responsive to receiving the first voltage.
12. The memory section control circuit of claim 9 , wherein the row address comprises a pre-decoded row address and further comprising a pre-decoder configured to receive an undecoded row address and provide the pre-decoded row address.
13. The memory section control circuit of claim 9 , wherein each of the global drivers is further configured to provide the voltage provided by the decoder voltage supply responsive to receipt of an inactive global row enable signal and to provide the third voltage responsive to receipt of an active global row enable signal.
14. The memory section control circuit of claim 9 , wherein the row address is generated by a self-refresh controller.
15. A method of refreshing memory, comprising:
providing a first voltage to a plurality of access line drivers corresponding to an active memory section to keep access lines coupled to the plurality of access line drivers inactive; and
providing a second voltage to a plurality of access line drivers corresponding to an inactive memory section to keep access lines coupled to the plurality of access line drivers inactive,
wherein the first voltage is greater than the second voltage and the second voltage is not provided to the plurality of access line drivers corresponding to the active memory section during an entire time the active memory section is active.
16. The method of claim 15 , further comprising providing a third voltage to another plurality of access line drivers corresponding to the active memory section to activate a selected one of the access lines coupled to the another plurality of access line drivers.
17. The method of claim 15 , further comprising deactivating the active section after refreshing the active memory section.
18. The method of claim 15 , wherein the active memory section comprises a first active memory section, and further comprising providing the first voltage to a plurality of access line drivers corresponding to a second active memory section to keep access lines coupled to the plurality of access line drivers of the second active memory section inactive.
19. The method of claim 15 , wherein the first voltage is a pumped voltage and the second voltage is a common voltage.
20. The method of claim 15 , further comprising refreshing a plurality of memory rows of the active memory section based, at least in part, on receipt of a plurality of phase enable signals.
21. A method of refreshing memory, comprising:
during a self-refresh operation, providing a pumped voltage to global drivers of an active memory section of the memory during an entire time the memory section is active, each of the plurality of global drivers associated with a respective plurality of word lines; and
during the self-refresh operation, providing a common voltage to global drivers of inactive memory sections of the memory, wherein the common voltage is lower than the pumped voltage.
22. The method of claim 21 wherein a plurality of memory sections are active during the self-refresh operation and the pumped voltage is provided to the global drivers of the plurality of memory sections that are active.
23. The method of claim 21 wherein providing a pumped voltage to global drivers of an active memory section of the memory during an entire time the memory section is active comprises maintaining providing the pumped voltage to the global drivers as different rows of memory in the active section are refreshed.
24. The method of claim 21 , further comprising coupling word lines of inactive memory sections to a deactivated word line voltage through word line drivers of the inactive memory sections.
25. A method of refreshing memory, comprising altering a voltage provided to a decoder responsive to a corresponding memory section becoming active or inactive, wherein the voltage provided to the decoder only changes at activation of the memory section and at deactivation of the memory section.
26. An apparatus, comprising:
a plurality of memory sections; and
a plurality of memory section control circuits, wherein each memory section control circuit is coupled to a respective one of the plurality of memory sections, wherein each memory section control circuit comprises a plurality of access line drivers, and wherein each of the access line drivers comprises a plurality of transistors having commonly coupled gates,
wherein, during an operation of the apparatus in which a memory section of the plurality of memory sections is active and a memory section of the plurality of memory sections is inactive, a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to the active memory section, a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to the inactive memory section control circuit, wherein the first voltage is greater than the second voltage, and a third voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to the active memory section, wherein the third voltage is lower than the second voltage.