Digit line comparison circuits
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.
1. An apparatus comprising:
a first plurality of row address register units, wherein a count of the first plurality of row address register units corresponds to a count of rows that are expected to have at least one memory cell unable to retain data, each of the first plurality of row address register units configured to store a row address corresponding to a respective row containing at least one memory cell unable to retain data;
a second plurality of row address register units, wherein a count of the second plurality of row address register units corresponds to a count of the first plurality of row address register units, each of the second plurality of row address register units operable to store a subset of bits of the row address stored in a respective first plurality of row address register units; and
a plurality of comparator units, each of the comparator units configured to receive a refresh row address and respectively coupled to a corresponding row address register unit of the first plurality of row address register units and a corresponding row address register unit of the second plurality of row address register units, each of the plurality of comparator units operable to compare the received refresh row address to the row address bits stored in the corresponding row address unit of the first plurality of row address register units and to the subset of bits stored in the corresponding row address unit of the second plurality of row address register units and generate a high match signal in the event of a match.
2. The apparatus of claim 1 , wherein at least one of the respective subset of bits stored in each of the second plurality of row address register units is different from at least another subset of bits stored in another of the second plurality of row address register units.
3. The apparatus of claim 1 , wherein a first high match signal is set by a first logic gate responsive to a match between the received refresh row address and the row address bits stored in the first plurality of row address register units, and a second high match signal is set by a second logic gate responsive to a match between the received refresh row address and the subset of bits stored in at least one of the second plurality of row address register units.
4. The apparatus of claim 3 , wherein each of the first logic gate and the second logic gate comprise an OR gate.
5. The apparatus of claim 3 , wherein a count of times the second high match signal is generated per refresh cycle depends on a count of bits stored as the subset of bits in each respective second plurality of row address register units.
6. The apparatus of claim 3 , further comprising a refresh row counter configured to generate the refresh row address.
7. The apparatus of claim 6 , wherein the refresh row counter is configured to increment responsive to the first high match signal being set, and further configured halt incrementing responsive to the first high match signal being cleared and the second high match signal being set.