Granted Patent B2

US 12,640,183 · App. 18/747,740 · Granted May 26, 2026

Inventors: Wonjun Choi (Boise, ID); Hyun Yoo Lee (Boise, ID)

Assignee: Micron Technology, Inc.

G11C11/40626

Abstract

Claims (44)

1 . An apparatus comprising:

a mode register comprising a refresh rate register;

a temperature sensor configured to provide a temperature code based on a measured temperature;

a targeted refresh queue configured to store a plurality of addresses, and configured to provide a refresh register shift signal with a value based on a number of the plurality of addresses; and

a refresh rate adjustment circuit configured to set a value of the refresh rate register based on the temperature code and the refresh register shift signal.

2 . The apparatus of claim 1 , wherein the refresh rate adjustment circuit is configured to select an initial value of the refresh rate register based on the temperature code and adjust the initial value a number of steps indicated by the refresh register shift signal to generate the value of the refresh rate register.

3 . The apparatus of claim 1 , wherein the targeted refresh queue is configured to provide the refresh register shift signal with a first value if it is below a first threshold, a second value if it is between the first threshold and a second threshold and a third value if it is above the second threshold.

4 . The apparatus of claim 1 , further comprising an aggressor detector circuit configured to provide an aggressor signal if a row address is determined to be an aggressor address, wherein responsive to the aggressor signal the targeted refresh queue is configured to store the row address as one of the plurality of addresses.

5 . The apparatus of claim 1 , further comprising:

a refresh state control circuit configured to perform one or more refresh operations responsive to a refresh signal, wherein the one or more refresh operations are normal refresh operations or targeted refresh operations; and

an address generator circuit configured to generate at least one refresh address based on a selected one of the stored plurality of addresses in the targeted refresh queue as part of the targeted refresh operation.

6 . The apparatus of claim 5 , wherein the refresh state control circuit is configured to change a ratio of the normal refresh operations and the targeted refresh operations based on the value of the refresh register shift signal.

7 . The apparatus of claim 5 , wherein responsive to the targeted refresh operation the targeted refresh queue is configured to provide the selected one of the plurality of addresses and remove it from the targeted refresh queue.

8 . A system comprising:

a memory comprising:

a mode register comprising a refresh rate register;

a temperature sensor configured to measure a temperature of the memory;

a refresh control circuit configured to perform at least one refresh operation responsive to a refresh signal, wherein the refresh control circuit includes a targeted refresh queue configured to store addresses; and

a refresh rate adjustment circuit configured to set a value of the refresh rate register based on the measured temperature and a number of addresses stored in the targeted refresh queue; and

a controller configured to provide the refresh signal at a rate based the value of the refresh rate register.

9 . The system of claim 8 , wherein the controller includes a refresh logic circuit configured to set a refresh interval based, in part, on the value of the refresh rate register and provide the refresh signal at least once in each of the refresh intervals.

10 . The system of claim 9 , wherein the value of the refresh rate register indicates a refresh multiplier and wherein and refresh logic multiplies a base refresh interval by the refresh multiplier.

11 . The system of claim 8 , wherein the refresh control circuit is configured to perform targeted refresh operations or normal refresh operations as the at least one refresh operation, and wherein the refresh control circuit is configured to set a ratio of the targeted and the normal refresh operations based on the number of addresses stored in the targeted refresh queue.

12 . The system of claim 8 , wherein the refresh rate adjustment circuit is configured to set an initial value based on the temperature and adjust the initial value a number of steps based on the number of addresses.

13 . The system of claim 8 , wherein the refresh control circuit includes an aggressor detector circuit configured to identify the addresses to store in the targeted refresh queue.

14 . A method comprising:

measuring a temperature of a memory device;

determining a number of addresses stored in a targeted refresh queue;

setting a value of a refresh rate register based on the measured temperature and the number of addresses.

15 . The method of claim 14 , further comprising:

reading the value of the refresh rate register; and

providing a refresh signal with timing based on the value of the refresh rate register.

16 . The method of claim 15 , further comprising performing one or more refresh operations responsive to the refresh signal.

17 . The method of claim 14 , further comprising determining a ratio of normal and targeted refresh operations based on the number of addresses stored in the targeted refresh queue.

18 . The method of claim 14 , further comprising:

determining if an address is an aggressor address; and

adding the aggressor address to the targeted refresh queue.

19 . The method of claim 14 , further comprising:

setting an initial value of the refresh rate register based on the measured temperature;

adjusting the initial value by a number of steps based on the number of addresses to generate an adjusted value; and

setting the adjusted value as the value of the refresh rate register.

20 . The method of claim 19 , further comprising:

comparing the number of addresses to a number of thresholds; and

setting the number of steps based on the comparing.

Assignments (1)

Continuity (2)

References Cited (400)