IP Library Granted Patent US 10,600,796
Granted Patent B2
US 10,600,796 · App. 15/624,422 · Granted Mar 24, 2020

Methods of forming staircase structures

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Quick Facts
Patent No.
US 10,600,796
App. No.
15/624,422
Granted
Mar 24, 2020
Kind
B2
Abstract

Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.

Claims (20)

1. A method of forming a staircase structure, comprising:

forming a slot through tiers of conductive structures and insulating structures on a material;

selectively forming recesses in the insulating structures;

forming a photoresist over the tiers and within the slot and within the recesses; and

conducting repeated trim acts of the photoresist to form stairs of the staircase structure.

2. The method of claim 1 , wherein forming a slot through tiers of conductive structures and insulating structures comprises forming the slot on an array region of the material.

3. The method of claim 1 , wherein forming a slot through tiers of conductive structures and insulating structures comprises forming the slot on a peripheral region of the material.

4. The method of claim 1 , wherein selectively forming recesses in the insulating structures comprises forming jagged sidewalls in the insulating structures.

5. The method of claim 1 , wherein forming a photoresist over the tiers and within the slot and recesses comprises forming the photoresist at a thickness of from about 1 μm to about 20 μm.

6. The method of claim 1 , further comprising treating surfaces of the insulating structures before forming the photoresist over the tiers.

7. The method of claim 1 , further comprising forming at least one contact structure on the stairs of the staircase structure.

8. The method of claim 1 , further comprising forming a channel material through at least a portion of the tiers of conductive structures and insulating structures.

9. The method of claim 8 , further comprising forming memory cells along a length of the channel material.

10. The method of claim 1 , wherein selectively forming recesses in the insulating structures comprises selectively forming the recesses in the insulating structures without forming the recesses in the conductive structures.

11. The method of claim 1 , wherein forming the slot through tiers of conductive structures and insulating structures comprises forming the slot through polysilicon structures and silicon dioxide structures.

12. The method of claim 1 , wherein forming the slot through tiers of conductive structures and insulating structures comprises forming the slot through tungsten structures and silicon dioxide structures.

13. The method of claim 1 , wherein forming the slot through tiers of conductive structures and insulating structures comprises forming the slot through polysilicon structures and silicon nitride structures.

14. The method of claim 1 , wherein selectively forming recesses in the insulating structures comprises increasing the surface area of the conductive structures.

15. The method of claim 1 , wherein selectively forming recesses in the insulating structures comprises selectively recessing material of the insulating structures adjacent to the slot at from about 30 nm to about 60 nm.

16. The method of claim 1 , wherein selectively forming recesses in the insulating structures comprises selectively removing portions of the insulating structures laterally adjacent the slot.

Assignments (8)
LICENSE Recorded Jun 6, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 067648/0893 →
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2017
From: KOTHARI, ROHIT; MCFARLAND, JASON C.; REECE, JASON; KEWLEY, DAVID A.; OLSON, ADAM L.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042727/0663 →