Constructions comprising stacked memory arrays
Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.
1. A construction, comprising:
a first memory array deck comprising first memory cells;
a second memory array deck over the first memory array deck, and comprising second memory cells;
wherein the first and second memory cells comprise chalcogenide;
wherein the chalcogenide of the second memory cells differs from the chalcogenide of the first memory cells in one or both of composition and thickness; and
wherein:
the first memory cells are laterally spaced from one another by first dielectric regions along a cross-section;
the second memory cells are laterally spaced from one another by second dielectric regions along the cross-section; and
the first dielectric regions differ from the second dielectric regions in one or more structural parameters; with said structural parameters including different materials and/or different thicknesses of materials.
2. The construction of claim 1 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and
the first insulative material liners are different thicknesses than the second insulative material liners.
3. The construction of claim 1 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and
the first insulative material liners are different compositions than the second insulative material liners.
4. The construction of claim 1 wherein the chalcogenide of the second memory cells differs from the chalcogenide of the first memory cells in both of composition and thickness.
5. The construction of claim 1 wherein the chalcogenide of the second memory cells differs from the chalcogenide of the first memory cells in composition.
6. The construction of claim 1 wherein the chalcogenide of the second memory cells differs from the chalcogenide of the first memory cells in thickness.