Constructions comprising stacked memory arrays
View Patent ↗Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.
1. A construction, comprising:
a first memory array deck;
a second memory array deck over the first memory array deck;
wherein the first and second memory array decks comprise phase change memory, and wherein the second memory array deck differs from the first memory array deck in one or more operating characteristics; and
wherein:
memory cells of the first memory array deck are laterally spaced from one another by first dielectric regions along a cross-section;
memory cells of the second memory array deck are laterally spaced from one another by second dielectric regions along the cross-section; and
the first dielectric regions differ from the second dielectric regions in one or more structural parameters; with said structural parameters including different materials and/or different thicknesses of materials.
2. The construction of claim 1 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of memory cells; and
the first insulative material liners are different thicknesses than the second insulative material liners.
3. The construction of claim 1 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of memory cells; and
the first insulative material liners are different compositions than the second insulative material liners.
4. The construction of claim 1 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of memory cells;
the first dielectric regions comprise a first insulator between the first insulative material liners;
the second dielectric regions comprise second insulative material liners along sidewalls of memory cells;
the second dielectric regions comprise a second insulator between the second insulative material liners; and
wherein the second insulator is a different composition relative to the first insulator.
5. The construction of claim 4 wherein:
the first insulator is solid and/or semisolid; and
the second insulator is gas.
6. The construction of claim 4 wherein:
the first and second insulative material liners comprising silicon nitride;
the first insulator comprises silicon dioxide; and
the second insulator is gas.
7. The construction of claim 4 wherein:
the first and second insulative material liners comprising silicon nitride;
the first insulator comprises silicon dioxide; and
the second insulator is a vacuum region.
8. A construction, comprising:
a first memory array deck;
a second memory array deck over the first memory array deck;
wherein the second memory array deck differs from the first memory array deck in one or more structural parameters; with said structural parameters including different materials and/or different thicknesses of materials; and
wherein:
first memory cells of the first memory array deck are laterally spaced from one another by first dielectric regions along a cross-section;
second memory cells of the second memory array deck are laterally spaced from one another by second dielectric regions along the crosssection; and
the first dielectric regions differ from the second dielectric regions in said one or more structural parameters.
9. The construction of claim 8 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and
the first insulative material liners are different thicknesses than the second insulative material liners.
10. The construction of claim 8 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and
the first insulative material liners are different compositions than the second insulative material liners.
11. The construction of claim 8 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the first dielectric regions comprise a first insulator between the first insulative material liners;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells;
the second dielectric regions comprise a second insulator between the second insulative material liners; and
wherein the second insulator is a different composition relative to the first insulator.
12. A construction, comprising:
a first series of access/sense lines extending along a first direction;
a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction;
a third series of access/sense lines over the second series of access/sense lines and extending along the first direction;
first memory cells between the first and second series of access/sense lines, the first memory cells being arranged in a first memory array deck and comprising first phase change material;
second memory cells between the second and third series of access/sense lines, the second memory cells being arranged in a second memory array deck and comprising second phase change material;
wherein the second memory array deck differs from the first memory array deck in one or more operating characteristics; and
wherein:
the first memory cells are laterally spaced from one another by first dielectric regions along a cross-section;
the second memory cells are laterally spaced from one another by second dielectric regions along the cross-section; and
the first dielectric regions differ from the second dielectric regions in one or more structural parameters with said structural parameters including different materials and/or different thicknesses of materials.
13. The construction of claim 12 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and
the first insulative material liners are different thicknesses than the second insulative material liners and/or are different compositions than the second insulative material liners.
14. The construction of claim 12 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the first dielectric regions comprise a first insulator between the first insulative material liners;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells;
the second dielectric regions comprise a second insulator between the second insulative material liners; and
wherein the second insulator is a different composition relative to the first insulator.