Memory configurations
In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.
1. A memory, comprising:
a group of series-coupled memory cells;
wherein a memory cell of the series-coupled memory cells comprises:
an access gate;
a control gate coupled to the access gate; and
a dielectric stack between the control gate and a semiconductor;
wherein the dielectric stack is to store a charge;
wherein the dielectric stack comprises an interface dielectric, a tunnel dielectric, a charge trap, and a blocking dielectric;
wherein the interface dielectric is adjacent to the semiconductor, the tunnel dielectric is adjacent to the interface dielectric, the charge trap is adjacent to the tunnel dielectric, and a blocking dielectric is adjacent to the charge trap; and
wherein a first storage dielectric is between the interface dielectric and the tunnel dielectric and a second storage dielectric is between the charge trap and the blocking dielectric.
2. The memory of claim 1 , wherein the control gate being coupled to the access gate comprises the control gate being capacitively coupled to the access gate by an additional dielectric.
3. The memory of claim 1 , wherein the group of series-coupled memory cells is below an upper surface of the semiconductor.
4. The memory of claim 1 , wherein the group of series-coupled memory cells is between a data line and a source.
5. The memory of claim 1 , wherein a channel of the memory cell of the series-coupled memory cells is between first and second conductive regions in the semiconductor.
6. The memory of claim 5 , wherein a channel of another memory cell of the series-coupled memory cells is between the second conductive region and a third conductive region in the semiconductor.
7. The memory of claim 1 , wherein the memory cell of the series-coupled memory cells comprises a USUM memory cell.
8. The memory cell of claim 1 , wherein the interface dielectric comprises OR-SiON, the first storage dielectric comprises i-SRN, the tunnel dielectric comprises HfSiON, the charge trap comprises GaN, the second storage dielectric comprises i-SRN, and the blocking dielectric comprises HfSiON or HfSiON and AL 2 O 3 .