Memory device having address and command selectable capabilities
View Patent ↗Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.
1. A method, comprising:
identifying a type of information associated with a first write command;
selecting, based at least in part on the type of the information, a first write circuit for executing the first write command; and
programming, by executing the first write command, the information to a first portion of a memory using the first write circuit.
2. The method of claim 1 , further comprising:
executing the first write command using the first write circuit based at least in part on selecting the first write circuit.
3. The method of claim 2 , wherein executing the first write command comprises applying a plurality of programming pulses.
4. The method of claim 2 , wherein executing the first write command comprises executing a verify process using the first write circuit.
5. The method of claim 4 , further comprising:
generating a program error pulse based at least in part on executing the verify process.
6. The method of claim 1 , further comprising:
identifying a second type of second information associated with a second write command;
selecting, based at least in part on the second type of the second information, a second write circuit for executing the second write command; and
executing the second write command using the second write circuit based at least in part on selecting the second write circuit.
7. The method of claim 6 , wherein executing the second write command comprises applying a programming pulse.
8. The method of claim 6 , wherein the second type of the second information comprises an operating system data or program data.
9. The method of claim 1 , wherein the type of the information comprises an operating system code or program code.
10. A memory device, comprising:
a memory array; and
a memory controller configured to:
identify a type of information associated with a first write command;
select, based at least in part on the type of the information, a first write circuit for performing the first write command; and
program, by executing the first write command, the information to a first portion of a memory using the first write circuit.
11. The memory device of claim 10 , wherein the memory controller is configured to:
execute the first write command using the first write circuit based at least in part on selecting the first write circuit; and
execute a verify process using the first write circuit based at least in part on executing the first write command.
12. The memory device of claim 11 , wherein the memory controller is configured to:
generate a program error pulse based at least in part on executing the first write command.
13. The memory device of claim 11 , wherein executing the first write command comprises applying a programming pulse using the first write circuit.
14. The memory device of claim 10 , wherein the memory controller is configured to:
identify a second type of second information associated with a second write command;
select, based at least in part on the second type of the second information, a second write circuit for performing the second write command; and
execute the second write command using the second write circuit based at least in part on selecting the second write circuit.
15. The memory device of claim 14 , wherein executing the second write command comprises applying one programming pulse using the second write circuit.
16. A system, comprising:
a memory array;
a processor configured to initiate a first write command for programming information to a first portion of the memory array; and
a memory controller configured to:
identify a type of information associated with the first write command;
select, based at least in part on the type of the information, a first write circuit for performing the first assess write command; and
program, by executing the first write command, the information to the first portion of the memory array using the first write circuit.
17. The system of claim 16 , wherein the memory controller is configured to:
identify a second type of second information associated with a second write command;
select, based at least in part on the second type of the second information, a second write circuit for performing the second write command; and
execute the second write command using the second write circuit based at least in part on selecting the second write circuit.