Error correction code for unidirectional memory
View Patent ↗A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed.
1. A method of generating coherent check words for programming memory cells to an intermediate state and to a final state without an intervening erase operation, the method comprising:
receiving a first data;
computing a first check code for the first data;
programming the first data and the first check code to a plurality of memory cells to change contents of the plurality of memory cells from an initial state to the intermediate state;
receiving a second data;
computing a second check code for the second data; and
programming the second data and the second check code to the plurality of memory cells without erasing the plurality of memory cells provided that contents of the second data and the second check code would be at the final state after programming.
2. The method of claim 1 , further comprising:
receiving user data; and
transforming the user data to the first data according to a transformation function, the first data being a same size as the user data.
3. The method of claim 2 , wherein transforming further comprises transforming according to a Gray code.
4. The method of claim 1 , wherein the plurality of memory cells comprise unidirectional non-volatile data storage cells.
5. The method of claim 1 , wherein the plurality of memory cells comprise flash memory cells.
6. The method of claim 1 , further comprising:
computing a first matrix multiplication of the first data and a matrix to generate a third check code;
computing a first matrix multiplication of the second data and the matrix to generate a fourth check code;
generating an inversion pattern based on a second matrix multiplication of an initial data comprising erased states and the matrix;
selectively inverting bits of the third check code based on the inversion pattern to generate the first check code, wherein the inversion pattern comprises a plurality of bits having a first state or a second state, wherein selectively inverting comprises inverting bits of the first check code corresponding to bit positions of the inversion pattern having the first state and not inverting bit positions corresponding to the second state; and
selectively inverting bits of the fourth check code based on the inversion pattern to generate the second check code.
7. The method of claim 6 , wherein the matrix comprises:
[
0010
1011
1111
1110
1011
0010
0001
1101
1110
1000
0100
1111
1101
1011
0111
0111
]
.
8. An apparatus comprising:
a controller configured to:
receive a first data;
compute a first check code for the first data;
program the first data and the first check code to a plurality of memory cells to change contents of the plurality of memory cells from an initial state to an intermediate state;
receive a second data;
compute a second check code for the second data; and
program the second data and the second check code to the plurality of memory cells without erasing the plurality of memory cells provided that contents of the second data and the second check code would be at a final state after programming.
9. The apparatus of claim 8 , wherein the controller is further configured to:
receive user data; and
transform the user data to the first data according to a transformation function, the first data being a same size as the user data.
10. The apparatus of claim 9 , wherein the controller is further configured to transform the user data according to a Gray code.
11. The apparatus of claim 8 , wherein the plurality of memory cells comprise unidirectional non-volatile data storage cells.
12. The apparatus of claim 8 , wherein the plurality of memory cells comprise flash memory cells.
13. The apparatus of claim 8 , wherein the controller is further configured to:
compute a first matrix multiplication of the first data and a matrix to generate a third check code;
compute a first matrix multiplication of the second data and the matrix to generate a fourth check code;
generate an inversion pattern based on a second matrix multiplication of an initial data comprising erased states and the matrix;
selectively invert bits of the third check code based on the inversion pattern to generate the first check code, wherein the inversion pattern comprises a plurality of bits having a first state or a second state, wherein selectively inverting comprises inverting bits of the first check code corresponding to bit positions of the inversion pattern having the first state and not inverting bit positions corresponding to the second state; and
selectively invert bits of the fourth check code based on the inversion pattern to generate the second check code.
14. The apparatus of claim 13 , wherein the matrix comprises:
[
0010
1011
1111
1110
1011
0010
0001
1101
1110
1000
0100
1111
1101
1011
0111
0111
]
.
15. A memory system comprising:
a plurality of memory cells; and
a controller configured to:
receive a first data;
compute a first check code for the first data;
program the first data and the first check code to the plurality of memory cells to change contents of the plurality of memory cells from an initial state to an intermediate state;
receive a second data;
compute a second check code for the second data; and
program the second data and the second check code to the plurality of memory cells without erasing the plurality of memory cells provided that contents of the second data and the second check code would be at a final state after programming.
16. The memory system of claim 15 , wherein the controller is further configured to:
receive user data; and
transform the user data to the first data according to a transformation function, the first data being a same size as the user data.
17. The memory system of claim 16 , wherein the controller is further configured to transform the user data according to a Gray code.
18. The memory system of claim 15 , wherein the plurality of memory cells comprise flash memory cells.
19. The memory system of claim 15 , wherein the controller is further configured to:
compute a first matrix multiplication of the first data and a matrix to generate a third check code;
compute a first matrix multiplication of the second data and the matrix to generate a fourth check code;
generate an inversion pattern based on a second matrix multiplication of an initial data comprising erased states and the matrix;
selectively invert bits of the third check code based on the inversion pattern to generate the first check code, wherein the inversion pattern comprises a plurality of bits having a first state or a second state, wherein selectively inverting comprises inverting bits of the first check code corresponding to bit positions of the inversion pattern having the first state and not inverting bit positions corresponding to the second state; and
selectively invert bits of the fourth check code based on the inversion pattern to generate the second check code.
20. The memory system of claim 19 , wherein the matrix comprises:
[
0010
1011
1111
1110
1011
0010
0001
1101
1110
1000
0100
1111
1101
1011
0111
0111
]
.