Semiconductor device assembly with die support structures
A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.
1. A semiconductor device assembly, comprising:
a first semiconductor die;
a second semiconductor die disposed over the first semiconductor die;
a plurality of die support structures between the first and second semiconductor dies, wherein each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them; and
a plurality of interconnects between the first and second semiconductor dies, wherein each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them, and wherein the first solder joint thickness is less than the second solder joint thickness,
wherein the stand-off pad of each of the plurality of die support structures extends from a first planar surface of the first semiconductor die by a greater amount than the conductive pad of each of the plurality of interconnects extends from the first planar surface, and
wherein the stand-off pillar of each of the plurality of die support structures extends from a second planar surface of the second semiconductor die by a greater amount than the conductive pillar of each of the plurality of interconnects extends from the second planar surface.
2. The semiconductor device assembly of claim 1 , wherein the stand-off pillar of each of the plurality of die support structures has a first width and wherein the conductive pillar of each of the plurality of interconnects has a second width of less than the first width.
3. The semiconductor device assembly of claim 1 , wherein the stand-off pad of each of the plurality of die support structures has a first width and wherein the conductive pad of each of the plurality of interconnects has a second width of less than the first width.
4. The semiconductor device assembly of claim 1 , wherein the stand-off pad of each of the plurality of die support structures has a first width and wherein the stand-off pillar of each of the plurality of die support structures has a second width of less than the first width.
5. The semiconductor device assembly of claim 1 , wherein the first solder joint thickness is less than 1 μm.
6. The semiconductor device assembly of claim 1 , wherein the plurality of die support structures include die support structures disposed about a periphery of the semiconductor device assembly.
7. The semiconductor device assembly of claim 1 , wherein the plurality of die support structures include die support structures disposed in a medial region of the semiconductor device assembly.
8. The semiconductor device assembly of claim 1 , wherein each of the plurality of die support structures is electrically isolated from other circuit elements of the semiconductor device assembly.
9. The semiconductor device assembly of claim 1 , wherein each of the plurality of die support structures further includes a first barrier material separating the stand-off pillar from the first bond material and a second barrier material separating the stand-off pad from the first bond material.
10. The semiconductor device assembly of claim 1 , wherein each of the plurality of interconnects further includes a first barrier material separating the conductive pillar from the second bond material and a second barrier material separating the conductive pad from the second bond material.
11. The semiconductor device assembly of claim 1 , wherein the first die comprises a memory die, and wherein the second die comprises one of a memory die and a logic die.