Power gate circuits for semiconductor devices
View Patent ↗Apparatuses and methods for gate power to circuits of semiconductor devices are described. An example apparatus includes a substrate, a first wiring and a second wiring, and a plurality of transistors. The first wiring may be supplied with a power voltage, and the first wiring is formed over the substrate and is elongating in a first direction. The second wiring may be formed between the substrate and the first wiring, and vertically overlapping the first wiring with the second wiring elongating in the first direction. The plurality of transistors are vertically coupled between the first wiring and the second wiring.
1. An apparatus, comprising:
a substrate;
a first wiring supplied with a power voltage, the first wiring being formed over the substrate and elongating in a first direction;
a second wiring formed between the substrate and the first wiring with vertically overlapping the first wiring, the second wiring elongating in the first direction;
a plurality of transistors vertically coupled between the first wiring and the second wiring;
a third wiring formed between the first wiring and the second wiring, the third wiring elongating in the first direction and being coupled to each of gates of the plurality of vertical transistors; and
an external terminal receiving a clock enable signal, wherein the third wiring is configured to receive a control signal of which logic level is controlled responsive to the clock enable signal.
2. The apparatus of claim 1 , wherein the third wiring has a plurality of apertures each penetrated by a corresponding one of sets of gates and bodies of the plurality of transistors.
3. The apparatus of claim 1 , further comprising a plurality of circuit blocks arranged in the first direction and under the second wiring, each of the plurality of circuit blocks being configured to be supplied with the power voltage from the second wiring.
4. An apparatus, comprising:
a substrate;
a first wiring supplied with a power voltage, the first wiring being formed over the substrate and elongating in a first direction;
a second wiring formed between the substrate and the first wiring with vertically overlapping the first wiring, the second wiring elongating in the first direction:
a plurality of transistors vertically coupled between the first wiring and the second wiring;
a third wiring between the first wiring and the second wiring;
a fourth wiring between the third wiring and the second wiring; and
a plurality of additional transistors each coupled between a corresponding one of the plurality of transistors and the second wiring;
wherein the third wiring elongates in the first direction and coupled to each of gates of the plurality of transistors and
wherein the fourth wiring elongates in the first direction and coupled to each of gates of the plurality of additional transistors.
5. The apparatus of claim 4 , further comprising an external terminal receiving a clock enable signal, wherein the third wiring is configured to receive a control signal of which logic level is controlled responsive to the clock enable signal.
6. The apparatus of claim 5 , wherein the fourth wiring is configured to receive the control signal.
7. The apparatus of claim 5 , further comprising a command decoder configured to output a row activate signal, wherein the fourth wiring is configured to receive an additional control signal of which logic level is controlled responsive to the row activate signal.
8. An apparatus, comprising:
a plurality of circuit blocks, each circuit block including circuits;
a first conductive structure configured to be provided a supply voltage;
a second conductive structure configured to provide power to the circuits of the plurality of circuit blocks;
a third conductive structure configured to be provided a second supply voltage;
a fourth conductive structure configured to provide power to the circuits of the plurality of circuit blocks;
a plurality of vertical transistors disposed between the first and second conductive structures and configured to provide power from the first conductive structure to the second conductive structure when activated, each of the plurality of vertical transistors including a respective gate included in a gate electrode disposed between the first and second conductive structures; and
a second plurality of vertical transistors disposed between the third and fourth conductive structures and configured to provide power from the third conductive structure to the fourth conductive structure when activated, each of the second plurality of vertical transistors including a respective gate included in a second gate electrode disposed between the third and fourth conductive structures.
9. The apparatus of claim 8 wherein each of the plurality of vertical transistors comprises a p-channel field effect transistor.
10. The apparatus of claim 8 wherein each of the plurality of vertical transistors comprises an n-channel field effect transistor.
11. The apparatus of claim 8 wherein each of the plurality of vertical transistors comprises a p-channel field effect transistor and wherein each of the second plurality of vertical transistors comprises an n-channel field effect transistor.
12. The apparatus of claim 8 wherein the first conductive structure, the second conductive structure, and the gate electrode extend lengthwise adjacent the circuits of the plurality of circuit blocks.
13. An apparatus, comprising:
a plurality of circuit blocks, each circuit block including circuits;
a first conductive structure configured to be provided a supply voltage;
a second conductive structure configured to provide power to the circuits of the plurality of circuit blocks; and
a plurality of pairs of vertical transistors disposed between the first and second conductive structures, each of the pairs of vertical transistors including stacked vertical transistors, the plurality of pairs of vertical transistors configured to provide power from the first conductive structure to the second conductive structure when activated, each of the plurality of pairs of vertical transistors including a first gate included in a first gate electrode disposed between the first and second conductive structures and further including a second gate included in a second gate electrode disposed between the first gate electrode and the second conductive structure.
14. The apparatus of claim 13 wherein the first conductive structure, the second conductive structure, the first gate electrode, and the second gate electrode are arranged vertically and adjacent the circuits of the plurality of circuit blocks.
15. The apparatus of claim 13 wherein the first and second gate electrodes are configured to receive a same signal to control activation of each of the plurality of pairs of vertical transistors.
16. The apparatus of claim 13 wherein the stacked vertical transistors of each of the pairs of vertical transistors share a post of semiconductor material that extends between the first and second conductive structures.
17. The apparatus of claim 13 wherein each the stacked vertical transistors of each of the pairs of vertical transistors includes a respective body having a circular cross-section.