Circuits, apparatuses, and methods for frequency division

1. An apparatus comprising:

first and second power lines;

a first node;

first and second transistors coupled in series between the first power line and the first node, each of the first and second transistors being of a first conductivity type;

a third transistor coupled between the first power line and the first node in parallel to the first and second transistors, the third transistor being of the first conductivity type; and

fourth and fifth transistors coupled in series between the first node and the second power line, each of the fourth and fifth transistors being of a second conductivity type;

wherein the first transistor is configured to receive a first signal, the first signal being configured to take a first level in a first operation mode to render the first transistor conductive, and the first signal being further configured to take a second level in a second operation mode to render the first transistor non-conductive;

wherein each of the second and fourth transistors is configured to receive a second signal, the second signal being configured to pulsate between first and second logic states; and

wherein each of the third and fifth transistors is configured to receive a third signal, the third signal being configured to take a third level in the first operation mode to render each of the third and fifth transistors non-conductive, and the third signal being further configured to pulsate between the first and second logic states in the second operation mode.

2. The apparatus of claim 1 , wherein the second signal is configured to pulsate between the first and second logic states at a first frequency, and the third signal is configured to pulsate between the first and second logic states in the second operation mode at a second frequency that is different from the first frequency.

3. The apparatus of claim 2 , wherein the first frequency is higher than the second frequency.

4. The apparatus of claim 2 , further comprising an output circuit coupled to the first node, the output circuit being configured to provide an output signal that pulsates at the first frequency in the first operation mode and at the second frequency at second frequency.

5. The apparatus of claim 4 , wherein the output circuit comprises a feedback circuit, the feedback circuit being configured to feed the output signal back to the first node.

6. The apparatus of claim 1 , wherein further comprises a keeper circuit, the keeper circuit being configured to keep the third signal at the third level at least in the first operation mode.

7. An apparatus comprising a clock circuit, the clock circuit being configured to, responsive to an input clock signal, provide an output clock signal that has a first frequency in a first operation mode and has a second frequency in a second operation mode, the first frequency being equal to a frequency of the input clock signal, and the second frequency being lower than the first frequency,

wherein the clock circuit comprises:

first and second power lines;

a first node configured to provide the output clock signal;

first and second transistors coupled in series between the first power line and the first node;

a third transistor coupled between the first power line and the first node in parallel to the first and second transistors; and

fourth and fifth transistors coupled in series between the first node and the second power line;

wherein the first transistor is configured to be rendered conductive in the first operation mode and non-conductive in the second operation mode;

wherein the second and fourth transistors are configured to operate complementally responsive to the input clock signal; and

wherein the third and fifth transistors are configured to operate complementally at the second frequency in the second operation mode and to be rendered non-conductive in the first operation mode.

8. The apparatus of claim 7 ,

wherein each of the first, second and third transistors is of a first conductivity type;

wherein each of the fourth and fifth transistors if a second conductivity type;

wherein gates of the second and fourth transistors are coupled in common to each other to receive the input clock signal; and

wherein gates of the third and fifth transistors are coupled in common to a second node.

9. The apparatus of claim 7 , wherein the clock circuit further comprises:

a sixth transistor coupled between the first power line and the second node in parallel to the third transistor, the sixth transistor being of the first conductivity type and configured to receive the input clock signal at agate thereof,

seventh, eighth and ninth transistors coupled in series between the second node and the second power line in parallel to the fourth and fifth transistors; each of the seventh, eighth and ninth transistors being of the second conductivity type, the seventh transistor having a gate coupled to a third node, the eighth transistor being configured to receive the input clock signal at agate thereof, and the ninth transistor being configured to be rendered conductive in the first operation mode and non-conductive in the second operation mode.

10. The apparatus of claim 9 , wherein the clock circuit further comprises:

eleventh and twelfth transistors coupled between the first power line and the third node, each of the eleventh and twelfth transistors being of the first conductivity type, the eleventh transistor having a gate coupled to a fourth node, and the twelfth transistor being configured to receive the input clock signal at agate thereof, and

a thirteenth transistor coupled between the third node and the second power line, the thirteenth transistor being of the second conductivity type and having a gate coupled to the fourth node.

11. The apparatus of claim 10 , wherein the clock circuit further comprises:

an output circuit coupled between the first node and the fourth node, the output circuit being configured to provide the output clock signal.

12. The apparatus of claim 11 , wherein the output circuit comprises:

an inverter coupled to the first node and configure to provide the output clock signal; and

a feedback circuit configured to feed the output clock signal back to the first node.

13. The apparatus of claim 8 , wherein the clock circuit further comprises

a keeper circuit coupled to the second node, the keeper circuit being configured to keep the second node at a level that renders each of the third and fifth transistors non-conductive at least in the second operation mode.

14. An apparatus comprising:

a first circuit configured to detect a difference in phase between a first clock signal and a second clock signal to provide a control signal indicative of the difference in phase;

a second circuit configured to provide a third clock signal responsive to the first clock signal and the control signal; and

a third circuit coupled between the first and second circuits, the third circuit configured to provide the second clock signal responsive to the third clock signal, the third circuit further configure to make a frequency of the second clock signal equal to a frequency of the third clock signal in a first operation state, and the third circuit further configure to make the frequency of the second clock signal different than the frequency of the third clock signal in a second operation state;

wherein the third circuit comprises:

first and second power lines;

a first node configured to provide the second clock signal;

first and second transistors coupled in series between the first power line and the first node, each of the first and second transistor being of a first conductivity type;

a third transistor coupled between the first power line and the first node in parallel to the first and second transistors, the third transistor being of the first conductivity type; and

fourth and fifth transistors coupled in series between the first node and the second power line, each of the fourth and fifth transistors being of a second conductivity type;

wherein the first transistor is configured to be rendered conductive in the first operation state and non-conductive in the second operation state;

wherein gates of the second and fourth transistors are coupled in common to receive the third clock signal; and

wherein gates of the third and fifth transistors are coupled in common to receive an intermediate signal relative to the second clock signal in the second operation state and to receive a level that renders each of the third and fifth transistors non-conductive in the first operation state.

15. The apparatus of claim 14 , wherein the third circuit is further configured to switch from the first operation state to the second operation state responsive to a relationship in phase between the first and third clock signals being locked.

16. The apparatus of claim 14 , wherein the second circuit comprises a delay line, the delay line configured to, responsive to the control signal, delay the first clock signal and to provide the third clock signal.

17. The apparatus of claim 16 , wherein the first circuit comprises:

a phase detector coupled to receive the first and second clock signals; and

a shift register coupled to the phase detector to provide the control signal.

18. The apparatus of claim 14 ,

wherein the third circuit is further configured to receive an enable signal;

wherein the first operation state is designated by a first logic level of the enable signal; and

wherein the second operation state is designated by a second logic level of the enable signal.

19. The apparatus of claim 14 ,

wherein the frequency of the second clock signal is smaller than the frequency of the third clock signal in the second operation state.

20. The apparatus of claim 19 ,

wherein the frequency of the third second clock signal is derived by dividing the frequency of the third clock signal by an integer more than 1.