NAND memory arrays, and devices comprising semiconductor channel material and nitrogen
View Patent ↗Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.
1. A device, comprising:
a gate spaced from a semiconductor channel material by a dielectric region;
a nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region; and wherein:
the semiconductor channel material comprises conductively doped polycrystalline silicon,
the nitrogen-containing material comprises silicon nitride;
the semiconductor channel material joining to the silicon nitride along an interface;
a volume of the semiconductor channel material comprising nitrogen to a concentration within a range of from about 0.1 atomic percent to about 5 atomic percent; said volume of the semiconductor channel material being within a distance of no greater than about 10Å from said interface; and
said volume of the semiconductor channel material comprising fluorine.
2. The device of claim 1 being a transistor, and having the semiconductor channel material extending between a pair of source/drain regions.
3. The device of claim 1 being a NAND memory cell, and having a charge-storage material on an opposing side of the dielectric region from the semiconductor channel material.
4. A device, comprising:
a stack of alternative insulative levels and conductive levels, the insulative levels comprising an insulative material;
a gate spaced from a semiconductor channel material by a dielectric region, the channel material being in direct contact with the dielectric region along an interface;
a volume of the semiconductor channel material comprising nitrogen to a concentration within a range of from about 0.1 atomic percent to about 5 atomic percent; said volume being within a range of from about 1 volume percent of the semiconductor channel material to about an entirety of the semiconductor channel material, the semiconductor channel material having a higher nitrogen concentration along a surface opposing the interface than a concentration of nitrogen along the interface; and
said volume of the semiconductor channel material additionally comprising fluorine.
5. A NAND memory array, comprising;
a stack of alternative insulative levels and conductive levels, the insulative levels comprising an insulative material;
a gate spaced from a semiconductor channel material by a dielectric region, the channel material being in direct contact with the dielectric region along an interface;
a volume of the semiconductor channel material comprising nitrogen to a concentration within a range of from about 0.1 atomic percent to about 5 atomic percent; said volume being within a range of from about 1 volume percent of the semiconductor channel material to about an entirety of the semiconductor channel material, the semiconductor channel material having a higher nitrogen concentration along a surface opposing the interface than a concentration of nitrogen along the interface;
said volume of the semiconductor channel material additionally comprising fluorine; and
a charge-storage material between the semiconductor channel material and the gate; the dielectric region being between the semiconductor channel material and the charge-storage material.
6. A memory array, comprising:
a vertical stack of alternating insulative layers and wordline layers;
a channel material extending vertically through the stack;
a charge-storage material between the channel material and the wordline layers;
a dielectric material between the channel material and the charge-storage material; and
the channel material comprising nitrogen and fluorine and having a first concentration of nitrogen along a first surface proximate the charge-storage material and a second concentration of nitrogen along a second surface that opposes the first surface, the second concentration of nitrogen being greater than the first concentration.
7. The memory array of claim 6 wherein a concentration of the nitrogen within the channel material changes along a lateral direction and is substantially constant along a vertical direction.
8. The memory array of claim 6 wherein the channel material is configured as a tube having an exterior surface along the stack and an interior surface in opposing relation to the exterior surface; and comprising a stoichiometric silicon nitride material directly against the interior surface of the tube.
9. The memory array of claim 6 wherein the channel material comprises silicon.
10. The memory array of claim 9 wherein the nitrogen is present within the channel material to a concentration within a range of from about 0.1 atomic percent to about 5 atomic percent.