Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors
Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.
1. An asymmetric capacitor, comprising
a ferroelectric material over a first electrode, wherein the ferroelectric material is configured to exhibit asymmetric switching characteristics;
a first interfacial material between the first electrode and the ferroelectric material;
a second electrode over the first interfacial material; and
a second interfacial material between the first interfacial material and the second electrode.
2. The asymmetric capacitor of claim 1 , wherein the ferroelectric material comprises a dopant selected from the group consisting of one or more of silicon, aluminum, zirconium, magnesium, strontium, gadolinium, and yttrium.
3. The asymmetric capacitor of claim 1 , wherein the first interfacial material comprises a different material than the second interfacial material.
4. The asymmetric capacitor of claim 1 , wherein the first interfacial material has a different thickness than the second interfacial material.
5. The asymmetric capacitor of claim 1 , wherein the ferroelectric material comprises hafnium dioxide, zirconium dioxide, lead zirconate titanate, or combinations thereof.
6. The asymmetric capacitor of claim 1 , wherein the first electrode comprises titanium nitride, titanium aluminum nitride, tantalum nitride, platinum, or combinations thereof.
7. The asymmetric capacitor of claim 1 , wherein the first interfacial material comprises an oxide of a material of the first electrode.
8. The asymmetric capacitor of claim 1 , wherein the second electrode comprises a different material than the first electrode.
9. The asymmetric capacitor of claim 1 , wherein the second electrode has a different thickness than the first electrode.
10. A method of operating a semiconductor device, the method comprising:
after applying one of a positive bias voltage or a negative bias voltage to an asymmetric memory cell comprising a capacitor exhibiting asymmetric properties, applying the other of the positive bias voltage or the negative bias voltage to the asymmetric memory cell, the positive bias voltage being different from the negative bias voltage.
11. The method of claim 10 , wherein applying the other of the positive bias voltage or the negative bias voltage to the asymmetric memory cell comprises applying a positive bias voltage having a different magnitude than the negative bias voltage.
12. The method of claim 10 , further comprising selecting the asymmetric memory cell to comprise a first electrode comprising titanium, a second electrode comprising titanium, an asymmetric ferroelectric material between the first electrode and the second electrode, and an interfacial material between the ferroelectric material and one of the first electrode and the second electrode.
13. The method of claim 10 , wherein applying the other of the positive bias voltage or the negative bias voltage to the asymmetric memory cell comprises applying the other of the positive bias voltage or the negative bias voltage across:
a ferroelectric material comprising hafnium oxide, zirconium oxide, or a combination thereof; and
an interfacial material.
14. The method of claim 10 , further comprising selecting the capacitor to comprise a first electrode comprising titanium aluminum nitride, a second electrode comprising titanium nitride, a ferroelectric material between the first electrode and the second electrode, and an interfacial material comprising aluminum nitride between the first electrode and the ferroelectric material.
15. The method of claim 10 , wherein applying the other of the positive bias voltage or the negative bias voltage to the asymmetric memory cell comprises applying one of a positive bias voltage and a negative bias voltage having a magnitude between about twenty-five percent and about ninety-nine percent of a magnitude of the other of the positive bias voltage and the negative bias voltage.
16. A memory cell, comprising:
an asymmetric capacitor comprising a first electrode, a ferroelectric material, and a second electrode and configured to exhibit asymmetric switching properties, wherein the asymmetric capacitor is configured to switch from a first polarization to a second polarization responsive to exposure to a first switching voltage and from the second polarization to the first polarization responsive to exposure to a second switching voltage that is different from the first switching voltage.
17. The memory cell of claim 16 , wherein an absolute value of the first switching voltage is different from an absolute value of the second switching voltage.
18. The memory cell of claim 16 , wherein the asymmetric capacitor comprises a first interfacial material between the first electrode and the ferroelectric material.
19. The memory cell of claim 18 , wherein the first interfacial material comprises titanium dioxide or aluminum nitride.
20. The memory cell of claim 18 , wherein the asymmetric capacitor further comprises a second interfacial material between the second electrode and the ferroelectric material.