IP Library Granted Patent US 10,090,282
Granted Patent B1
US 10,090,282 · App. 15/621,955 · Granted Oct 2, 2018

Semiconductor device assemblies with lids including circuit elements

Inventor: Thomas H. Kinsley (Boise, ID)
Assignee: Micron Technology, Inc.
H01L25/0657H01L2225/06548H01L2225/06582H01L2225/06589
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Quick Facts
Patent No.
US 10,090,282
App. No.
15/621,955
Granted
Oct 2, 2018
Kind
B1
Abstract

A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies. The annular lower lid includes a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening. The semiconductor device assembly further includes a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts. The semiconductor device assembly further includes the upper lid disposed over the annular lower lid and the stack of semiconductor dies.

Claims (29)

1. A semiconductor device package, comprising:

a stack of semiconductor dies over a substrate;

the substrate including a plurality of electrical contacts;

an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies, the annular lower lid including a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening;

a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts; and

the upper lid disposed over the annular lower lid and the stack of semiconductor dies,

wherein the opening is a first opening and the circuit element is a first circuit element, and wherein the annular lower lid includes a second opening in the outer surface, and wherein the semiconductor device package includes a second circuit element disposed in the second opening and electrically coupled to at least a second one of the plurality of electrical contacts.

2. The semiconductor device package of claim 1 , wherein the lower lid comprises a metal.

3. The semiconductor device package of claim 1 , wherein the upper lid comprises a metal.

4. The semiconductor device package of claim 1 , wherein the first circuit element is configured for wireless communication.

5. The semiconductor device package of claim 1 , wherein the first circuit element is a sensor.

6. The semiconductor device package of claim 1 , wherein the semiconductor device package includes a third circuit element disposed in the first opening and electrically coupled to at least a third one of the plurality of electrical contacts.

7. The semiconductor device package of claim 1 , wherein the lower lid includes at least one via electrically coupling the first circuit element to the first one of the plurality of electrical contacts.

8. The semiconductor device package of claim 7 , wherein the at least one via is electrically isolated from the lower lid.

9. The semiconductor device package of claim 7 , wherein the at least one via is electrically coupled to the first one of the plurality of electrical contacts by a solder joint.

10. A semiconductor device package, comprising:

a stack of semiconductor dies over a substrate;

the substrate including a plurality of electrical contacts;

a lid disposed over the substrate and surrounding the die stack, the lid including a lower surface coupled to the substrate, an upper surface above the stack of semiconductor dies, and an outer surface in which is formed an opening; and

a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts,

wherein the opening is a first opening and the circuit element is a first circuit element, and wherein the lid includes a second opening in the outer surface, and wherein the semiconductor device package includes a second circuit element disposed in the second opening and electrically coupled to at least a second one of the plurality of electrical contacts.

11. The semiconductor device package of claim 10 , wherein the lid comprises a metal.

12. The semiconductor device package of claim 10 , wherein the first circuit element is configured for wireless communication.

13. The semiconductor device package of claim 10 , wherein the first circuit element is a sensor.

14. The semiconductor device package of claim 10 , wherein the semiconductor device package includes a third circuit element disposed in the first opening and electrically coupled to at least a third one of the plurality of electrical contacts.

15. The semiconductor device package of claim 10 , wherein the lid includes at least one via electrically coupling the first circuit element to the first one of the plurality of electrical contacts.

16. The semiconductor device package of claim 15 , wherein the at least one via is electrically isolated from the lid.

17. The semiconductor device package of claim 15 , wherein the at least one via is electrically coupled to the first one of the plurality of electrical contacts by a solder joint.

18. The semiconductor device package of claim 10 , wherein the lid is a two-piece lid comprising an annular lower lid and an upper lid.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050700/0535 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0393 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2018
From: KINSLEY, THOMAS H.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046063/0633 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION
Reel/Frame 043483/0686 →
SUPPLEMENT NO. 5 TO PATENT SECURITY AGREEMENT Recorded Aug 8, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 043482/0776 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2017
From: KINSLEY, THOMAS H.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042697/0748 →
Cited By (1)
US 12,408,260