Apparatuses and methods for providing data to a configurable storage area
Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.
1. An apparatus, comprising:
an array having a storage area;
an extended address register including a plurality of configuration bits that define a partition of the storage area;
a buffer configured to store data in a plurality of cache lines, the data including data to be stored in the storage area; and
a memory control circuit configured to identify data to be stored in the storage area, and responsive, at least in part, to a flush command, cause the data identified to be stored in the storage area of the array,
wherein the memory control circuit is further configured to interrupt the flush command to prepare for a read command or a write command and resume the flush command once the read command or the write command is performed.
2. The apparatus of claim 1 wherein the memory control circuit is configured to interrupt the flush command responsive to having a maximum variable latency period for the read and write commands.
3. The apparatus of claim 1 wherein the partition of the storage area comprises size and/or offset relative to an address.
4. The apparatus of claim 1 , further comprising:
a flag status register including a flush bit, the flush bit configured to indicate whether the buffer includes data intended to be stored in the storage area.
5. The apparatus of claim 1 , wherein the memory control unit is further configured to identify data intended to be stored in the storage area based, at least in part, on an address associated with the data intended to be stored in the storage area.
6. An apparatus, comprising:
an array having a storage area, the storage area having a size based on a first plurality of configuration bits and an offset based on a second plurality of configuration bits;
a buffer coupled to the array and comprising a plurality of cache lines, at least one of the plurality of cache lines configured to provide data to the storage area; and
a memory control unit coupled to the buffer and configured to cause the at least one cache line to provide the data to the storage area responsive, at least in part, to a flush command, wherein the memory control circuit is further configured to interrupt the flush command to prepare for a memory command and resume the flush command once the memory command is performed.
7. The apparatus of claim 6 wherein the second plurality of configuration bits indicate an offset for the storage area relative to the size of the array.
8. The apparatus of claim 6 wherein the configuration bits indicate an offset for the storage area relative to the size of the array.
9. The apparatus of claim 6 wherein the configuration bits indicate an offset based at least in part on an address.
10. The apparatus of claim 6 wherein the plurality of configuration bits indicate a size of the storage area based on the size of the array.
11. The apparatus of claim 6 wherein the plurality of configuration bits indicate a size of the storage area based on bytes, blocks, and/or address ranges.
12. The apparatus of claim 6 , wherein the at least one cache line includes a usage field configured to indicate whether the at least one cache line includes data to be provided to the storage area.
13. The apparatus of claim 6 , wherein the memory control unit is configured to adjust the size by modifying the first plurality of configuration bits and adjust the offset by modifying the second plurality of configuration bits.
14. The apparatus of claim 6 , further comprising:
an extended address register configured to store the configuration bits.
15. A method, comprising:
storing write data in a cache line of a buffer, the write data including write data associated with a storage area of an array;
providing the write data associated with the storage area to the storage area responsive, at least in part, to a flush command;
interrupting providing the write data to the storage area to prepare for a read command or a write command; and
resuming providing the write data to the storage area once the read command or the write command is performed,
wherein at least one of a size or offset of the storage area is based, at least in part, on a plurality of configuration bits.
16. The method of claim 15 , further comprising:
providing the state of a flush bit responsive, at least in part, to receipt of a read flag status register command.
17. The method of claim 15 , wherein providing the write data associated with the storage area to the storage area responsive, at least in part, to a flush command comprises:
storing the write data in non-volatile memory.
18. The apparatus of claim 15 , further comprising:
updating the plurality of configuration bits to change the size of the storage area.
19. The apparatus of claim 15 , further comprising:
updating the configuration bits to change the offset of the storage area.
20. The apparatus of claim 19 wherein the configuration bits are updated responsive to a command provided by a host.