Apparatuses and methods for providing constant DQS-DQ delay in a memory device

1. An apparatus, comprising:

a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory;

a second adjustable delay line included in the data strobe signal pathway; and

a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway, wherein the timing control circuit comprises:

a phase detector coupled to receive a fust input from the first adjustable delay line and a second input front die data strobe signal pathway and to generate an output signal that is indicative of a phase difference between the first and second inputs, and

a shift control logic coupled to receive the output signal of the phase detector and to generate respective shift commands that adjust the first and second adjustable delay lines.

2. The apparatus of claim 1 , wherein during memory operations where data is written to the memory, the first adjustable delay line is disabled from responding to shift commands from the shift control logic and the second adjustable delay line is enabled to respond to shift commands from the shift control logic.

3. The apparatus of claim 1 , wherein:

the first adjustable delay line includes an input that is coupled to an end of the data strobe signal pathway that is proximate to a data strobe pad; and

the second input to the phase detector is coupled to an end of the data strobe signal pathway that is proximate to a data latch.

4. The apparatus of claim 1 , wherein:

the first adjustable delay line includes an input that is coupled to an end of the data strobe signal pathway that is proximate to a data latch; and

the second input to the phase detector is coupled to an end of the data strobe signal pathway that is proximate to a data strobe pad.

5. The apparatus of claim 1 , wherein the first adjustable delay line is regulated.

6. The apparatus of claim 1 , wherein the delay provided by the first adjustable delay line is set during an initialization procedure that includes a coarse lock portion and a static lock portion.

7. The apparatus of claim 6 , wherein the coarse lock portion of the initialization procedure includes a training procedure that measures the loop delay of the data strobe signal pathway.

8. The apparatus of claim 1 , wherein the second adjustable delay line comprises:

a coarse delay component that is configured to provide a leading signal that defines a lower bound of delay and a lagging signal that defines an upper bound of delay; and

a fine delay component coupled to the coarse delay component and configured to provide a delay for the second adjustable delay line that is within the upper and lower bounds defined by the coarse delay line.

9. The apparatus of claim 1 , wherein the data strobe signal pathway further comprises a clock distribution tree.

10. An apparatus, comprising:

an unregulated delay line configured to receive a data strobe signal and to provide a delayed data strobe signal internal to a memory;

a clock distribution tree coupled to receive the delayed data strobe signal from the unregulated delay line and to distribute the delayed data strobe to at least one data latch for clocking of data corresponding to the data strobe;

a timing control circuit coupled to the unregulated delay line and configured to adjust an amount of delay provided by the unregulated delay line as the data is written to the memory; and

a regulated delay line coupled to the timing control circuit and configured to provide a delay corresponding to a loop delay of a data strobe signal pathway that includes the unregulated delay line and the clock distribution tree;

wherein the timing control circuit is configured to adjust the amount of delay provided by the unregulated delay line responsive to output from the regulated delay line.

11. The apparatus of claim 10 , wherein the timing control circuit comprises:

a phase detector coupled to receive a first input from the regulated delay line and a second input from the data strobe signal pathway and to generate an output signal that is indicative of a phase difference between the first and second inputs; and

a shift control logic coupled to receive the output signal of the phase detector and to generate responsive shift commands that adjust the regulated and unregulated delay lines.

12. The apparatus of claim 11 , wherein the shift control logic adjusts the regulated delay line during an initialization procedure and not during memory operations when data is written to the memory.

13. A method, comprising:

generating a first data strobe input through a regulated delay line;

generating a second data strobe input through a data strobe signal pathway that includes an unregulated delay line and a clock distribution tree;

receiving the first and second data strobe inputs at a phase detector;

determining, by the phase detector, a phase difference between the first and second data strobe inputs;

generating a shift command by a shift control logic based on the phase difference determined by the phase detector; and

providing the shift command to an unregulated delay line so as to adjust an amount of delay that the unregulated delay line provides to a data strobe as data corresponding to the data strobe is received.

14. The method of claim 13 , further comprising:

setting a delay for the regulated delay line through an initialization procedure that includes a coarse lock portion and a static lock portion.

15. The method of claim 14 , wherein the coarse lock portion of the initialization procedure includes a training procedure that measures a loop delay of the data strobe signal pathway.

16. The method of claim 13 , wherein providing the shift command to the delay line includes providing the shift command to at least one of a coarse delay line and a fine phase mixer.

17. An apparatus, comprising:

a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, wherein the delay provided by the first adjustable delay line is set during an initialization procedure that includes a coarse lock portion and a static lock portion;

a second adjustable delay line included in the data strobe signal pathway; and

a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.

18. The apparatus of claim 17 , wherein the coarse lock portion of the initialization procedure includes a training procedure that measures the loop delay of the data strobe signal pathway.

19. An apparatus, comprising:

a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory;

a second adjustable delay line included in the data strobe signal pathway, the second adjustable delay line comprising:

a coarse delay component that is configured to provide a leading signal that defines a lower bound of delay and a lagging signal that defines an upper bound of delay, and

a fine delay component coupled to the coarse delay component and configured to provide a delay for the second adjustable delay line that is within the upper and lower bounds defined by the coarse delay line; and

a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.