METHOD, SYSTEM, AND DEVICE FOR L-SHAPED MEMORY COMPONENT

1 . (canceled)

2 . A memory device, comprising:

a storage cell comprising an L-shaped storage component having an first portion extending from a first electrode positioned below the L-shaped storage component to a second electrode positioned above or on the L-shaped storage component, the storage cell further comprising a selector material positioned above or on the second electrode and a third electrode positioned above or on the selector material, wherein the first portion of the L-shaped storage component comprises a reduced size storage component in a first dimension.

3 . The memory device of claim 2 , wherein the storage cell comprises a phase change memory with selector (PCMS) storage cell.

4 . The memory device of claim 3 , wherein the storage cell further comprises an integrated self-heating structure.

5 . The memory device of claim 2 , wherein the reduced size storage component of the L-shaped storage component in the first dimension is partially or substantially affected by a deposition of storage component material on an first wall of a trench located in a dielectric material.

6 . The memory device of claim 5 , wherein the reduced size storage component of the L-shaped storage component in the first dimension is at least partially affected by a thickness of the L-shaped storage component.

7 . The memory device of claim 6 , wherein a size of the L-shaped storage component in a second dimension is at least partially affected by an additional trench.

8 . The memory device of claim 7 , wherein the additional trench is positioned in a direction approximately orthogonal to the trench located in the dielectric material.

9 . A memory device, comprising:

a first trench formed in a dielectric material, the first trench extending in a first direction and;

a second trench formed in the dielectric material, the second trench extending in a second direction orthogonal to the first direction;

one or more storage components positioned along the first direction in the first trench;

a first electrode material positioned over the one or more storage components;

a third trench extending in the first direction through the first electrode material;

a plurality of electrodes positioned along the first direction in the third trench; and

a fourth trench extending in the second direction through the first electrode material and through at least a portion of the dielectric material.

10 . The memory device of claim 9 , further comprising:

a selector material positioned over the first electrode material; and

a second electrode material over the selector material, wherein the second trench and the third trench each extend through the selector material and the second electrode material.

11 . The memory device of claim 10 , further comprising:

a bottom electrode material positioned under the dielectric material, wherein the fourth trench extends through at least a portion of the bottom electrode material.

12 . The memory device of claim 11 , further comprising:

a second memory device positioned over the second electrode material, the second memory device comprising:

a first plurality of electrodes each in electronic communication with at least the second electrode material;

one or more additional storage components positioned over each of the first plurality of electrodes; and

a second plurality of electrodes positioned over the one or more storage components, wherein the second plurality of electrodes is in electronic communication with the one or more additional storage components positioned over the first plurality of electrodes.

13 . The memory device of claim 12 , further comprising:

a plurality of memory devices positioned over the second memory device, the plurality of memory devices each comprising:

a third plurality of electrodes;

one or more additional storage components positioned over the third plurality of electrodes; and

a fourth plurality of electrodes positioned over each of the one or more storage components, wherein the fourth plurality of electrodes is in electronic communication with the one or more storage components positioned over the third plurality of electrodes.

14 . The memory device of claim 10 , wherein each of one or more additional storage components comprises:

a first portion extending in the first direction; and

a second portion extending in the second direction, wherein the second direction is orthogonal to the first direction.

15 . The memory device of claim 14 , wherein the second portion of each of the at one or more additional storage components is in contact with at least a portion of the first electrode material.

16 . The memory device of claim 9 , wherein each of the one or more storage components comprise a chalcogenide material.

17 . A memory device, comprising:

a first trench formed in a dielectric material, the first trench extending in a first direction;

a plurality of second trenches formed in the dielectric material, each of the plurality of second trenches extending in a second direction different than the first direction;

a plurality of storage components positioned along the first direction in the first trench;

a first electrode material positioned over each of the plurality of storage components;

a plurality of third trenches extending in the first direction through the first electrode material;

a plurality of electrodes positioned along the first direction in each of the plurality of third trenches;

a plurality of fourth trenches extending in the second direction through the first electrode material and at through least a portion of the dielectric material; and

a processor in electronic communication with each of the plurality of storage components, wherein the processor is operable to:

transmit a memory access command to each of the plurality of storage components; and

access each of the plurality of storage components in response to the memory access command.

18 . The memory device of claim 17 , wherein the processor is further operable to:

transmit a word line select signal to the first electrode material; and

transmit a bit line select signal to the first electrode material, wherein the accessing each of the plurality of storage components is based at least in part on the word line select signal and the bit line select signal.

19 . The memory device of claim 17 , further comprising:

a plurality of memory devices positioned over the memory device, the plurality of memory devices each comprising:

a first plurality of electrodes;

one or more additional storage components positioned over the first plurality of electrodes; and

a second plurality of electrodes positioned over each of the one or more additional storage components, wherein the second plurality of electrodes is in electronic communication with each of the one or more additional storage components positioned over the first plurality of electrodes, wherein the processor is further operable to:

transmit the memory access command to each of the one or more additional storage components of each of the plurality of memory devices; and

access each of the one or more additional storage components of each of the plurality of memory devices in response to the memory access command.

20 . The memory device of claim 19 , wherein each of the one or more additional storage components includes a phase change memory with selector (PCMS) storage cell.

21 . The memory device of claim 19 , wherein each of the one or more additional storage components includes an integrated self-heating structure.