Semiconductor device assembly with surface-mount die support structures
A semiconductor device assembly is provided. The assembly includes a first package element and a second package element disposed over the first package element. The assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. The assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. The first height is about equal to a sum of the solder joint thickness and the second height.
1. A semiconductor device assembly, comprising:
a first package element;
a second package element disposed over the first package element, the second package element including a plurality of conductive features and a passivation material configured to provide electrical isolation between the conductive features;
a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures is a monolithic structure with a first height, a lower surface mounted to the first package element and an upper surface in direct contact with the passivation material of the second package element, and is electrically isolated from other circuit elements of the semiconductor device assembly; and
a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a first conductive element on the first package element, a second conductive element on one of the plurality of conductive features of the second package element, and a bond material between the first and second conductive elements,
wherein each of the plurality of die support structures has a greater width than each of the plurality of interconnects, and
wherein at least one of the plurality of die support structures includes a discrete capacitor electrically connected to other circuit elements in the first package element.
2. The semiconductor device assembly of claim 1 , wherein the plurality of die support structures include die support structures disposed about a periphery of the semiconductor device assembly.
3. The semiconductor device assembly of claim 1 , wherein the plurality of die support structures include die support structures disposed in a medial region of the semiconductor device assembly.
4. The semiconductor device assembly of claim 1 , wherein each of the plurality of die support structures is surface-mounted to one or more mounting pads on the first package element.
5. The semiconductor device assembly of claim 1 , wherein the first package element comprises a logic die, and wherein the second package element comprises a memory die.
6. The semiconductor device assembly of claim 1 , wherein the first package element comprises a support substrate, and wherein the second package element comprises a logic die.