Device having multiple switching buffers for data paths controlled based on IO configuration modes
View Patent ↗A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.
1. An apparatus comprising:
a first memory bank;
a second memory bank, the second memory bank and the first memory bank being arranged in line a first direction;
a plurality of first data lines coupled to transfer a plurality of first data read from the first memory bank, the plurality of first data lines extending in the first direction; and
a plurality of second data lines coupled to transfer a plurality of second data read from the second memory bank, the plurality of second data lines extending in the first direction and extending, at least in part, in parallel to the plurality of first data lines;
wherein the plurality of first data lines do not transfer any data read from the second memory bank.
2. The apparatus of claim 1 , wherein each of the plurality of second data lines comprises a first portion extending directly adjacent to a corresponding one of the plurality of first data lines.
3. The apparatus of claim 2 , wherein each of the plurality of second data lines comprises a second portion extending directly adjacent to a corresponding one of voltage lines.
4. The apparatus of claim 3 , further comprising a plurality of first buffer circuits each coupled between the first and second portions of a corresponding one of the plurality of second data lines.
5. The apparatus of claim 4 , further comprising a plurality of second buffer circuits and a plurality of third buffer circuits;
wherein the first portion of each of the plurality of second data lines is coupled to a corresponding one of the plurality of second buffer circuits; and
wherein each of the plurality of first data lines is coupled to a corresponding one of the plurality of third buffer circuits.
6. The apparatus of claim 1 , further comprising:
a first main amplifier circuit configured to drive the plurality of first data lines based on the plurality of first data; and
a second main amplifier circuit configured to drive the plurality of second data lines based on the plurality of second data.
7. The apparatus of claim 6 , wherein the first main amplifier circuit and the first memory bank are arranged in line in a second direction crossing the first direction and the second main amplifier circuit and the second memory bank are arranged in line in the second direction.
8. The apparatus of claim 1 , further comprising:
a third memory bank, the third memory bank and the first memory bank being arranged in line in a second direction crossing the first direction;
a fourth memory bank, the fourth memory bank and the second memory bank being arranged in line in the second direction;
a plurality of third data lines coupled to transfer a plurality of third data read from the third memory bank, the plurality of third data lines extending in the first direction; and
a plurality of fourth data lines coupled to transfer a plurality of fourth data read from the fourth memory bank, the plurality of fourth data lines extending in the first direction and extending, at least in part, in parallel to the plurality of third data lines;
wherein the plurality of third data lines do not transfer any data read from the fourth memory bank.
9. The apparatus of claim 8 , wherein each of the plurality of fourth data lines comprises a third portion extending directly adjacent to a corresponding one of the plurality of third data lines.
10. The apparatus of claim 9 , wherein each of the plurality of fourth data lines comprises a fourth portion extending directly adjacent to a corresponding other one of the plurality of fourth data lines.
11. The apparatus of claim 10 , further comprising a plurality of fourth buffer circuits each coupled between the third and fourth portions of a corresponding one of the plurality of fourth data lines.
12. The apparatus of claim 11 , further comprising a plurality of fifth buffer circuits and a plurality of sixth buffer circuits;
wherein the third portion of each of the plurality of fourth data lines is coupled to a corresponding one of the plurality of fifth buffer circuits; and
wherein each of the plurality of third data lines is coupled to a corresponding one of the plurality of sixth buffer circuits.
13. An apparatus comprising:
a first memory bank;
a second memory bank arranged directly adjacent to the first memory bank;
a plurality of first data lines coupled to transfer a plurality of first data read from the first memory bank; and
a plurality of second data lines coupled to transfer a plurality of second data read from the second memory bank, the plurality of second data lines extending, at least in part, in parallel to the plurality of first data lines;
wherein the plurality of first data lines do not transfer any data read from the second memory bank.
14. The apparatus of claim 13 , wherein each of the plurality of second data lines comprises a first portion extending directly adjacent to a corresponding one of the plurality of first data lines.
15. The apparatus of claim 14 , wherein each of the plurality of second data lines comprises a second portion extending directly adjacent to a corresponding one of voltage lines.
16. The apparatus of claim 15 , further comprising a plurality of first buffer circuits each coupled between the first and second portions of a corresponding one of the plurality of second data lines.
17. The apparatus of claim 16 , further comprising a plurality of second buffer circuits and a plurality of third buffer circuits;
wherein the first portion of each of the plurality of second data lines is coupled to a corresponding one of the plurality of second buffer circuits; and
wherein each of the plurality of first data lines is coupled to a corresponding one of the plurality of third buffer circuits.
18. The apparatus of claim 13 , further comprising:
a first main amplifier circuit configured to drive the plurality of first data lines based on a plurality of first data stored in the first memory bank; and
a second main amplifier circuit configured to drive the plurality of second data lines based on a plurality of second data stored in the second memory bank.