Self-reference sensing for memory cells

1. A method, comprising:

applying a first read voltage to a first access line of a ferroelectric memory cell during a first portion of an access operation, wherein the ferroelectric memory cell comprises a ferroelectric capacitor, a first transistor in electronic communication with a first plate of the ferroelectric capacitor and with the first access line, and a second transistor in electronic communication with a second plate of the ferroelectric capacitor and with a second access line;

coupling the second access line of the ferroelectric memory cell with a first node of a latch during the first portion of the access operation;

applying a second read voltage to the second access line of the ferroelectric memory cell during a second portion of the access operation that is different than the first portion;

coupling the first access line of the ferroelectric memory cell with a second node of the latch during the second portion of the access operation;

comparing a first voltage at the first node of the latch to a second voltage at the second node of the latch during a third portion of the access operation; and

determining a logic value associated with the ferroelectric memory cell based at least in part on comparing the first voltage and the second voltage.

2. The method of claim 1 , further comprising:

grounding or virtually grounding the first access line and the second access line after applying the first read voltage, wherein the second read voltage is applied after the grounding or virtual grounding.

3. The method of claim 1 , further comprising:

writing the logic value to the ferroelectric memory cell during a fourth portion of the access operation.

4. The method of claim 1 , wherein applying the first read voltage generates a read signal and applying the second read voltage generates a reference signal, and wherein the logic value is determined based at least in part on a comparison of the read signal and the reference signal.

5. The method of claim 4 , wherein a difference between the first read voltage and the second read voltage is based at least in part on a difference between the read signal and the reference signal.

6. The method of claim 1 , wherein the first read voltage and the second read voltage are a same voltage.

7. The method of claim 1 , wherein the second read voltage is different than the first read voltage.

8. The method of claim 1 , wherein a third voltage of the second access line during the first portion of the access operation is based at least in part on a polarization of the ferroelectric memory cell.

9. The method of claim 8 , wherein a fourth voltage of the first access line during the second portion of the access operation is less than the third voltage of the second access line.

10. An electronic memory apparatus, comprising: a ferroelectric

memory cell that comprises a ferroelectric capacitor, a first transistor in electronic communication with a first plate of the ferroelectric capacitor and with a first access line, and a second transistor in electronic communication with a second plate of the ferroelectric capacitor and with a second access line; and

a controller in electronic communication with the ferroelectric memory cell, wherein the controller is configured to:

apply a first read voltage to the first access line during a first portion of an access operation;

couple the second access line of the ferroelectric memory cell with a first node of a latch during the first portion of the access operation;

apply a second read voltage to the second access line during a second portion of the access operation that is different than the first portion;

couple the first access line of the ferroelectric memory cell with a second node of the latch during the second portion of the access operation;

compare a first voltage at the first node of the latch to a second voltage at the second node of the latch during a third portion of the access operation; and

determine a logic value associated with the ferroelectric memory cell based at least in part on comparing the first voltage and the second voltage.

11. The electronic memory apparatus of claim 10 , further comprising:

a first switching component and a second switching component, wherein the controller is configured to:

apply the first voltage to the first access line via the first switching component; and

apply the second voltage to the second access line via the second switching component.

12. The electronic memory apparatus of claim 11 , wherein the first access line is in electronic communication with the latch at the first node, the second access line is in electronic communication with the latch at the second node, and wherein the first node and the second node are in electronic communication via a third switching component.

13. The electronic memory apparatus of claim 12 , wherein the controller is configured to:

activate the first switching component in electronic communication with the first access line;

activate the second switching component in electronic communication with the second access line; and

compare the first voltage and the second voltage at the latch based at least in part on activating the first switching component and the second switching component.

14. The electronic memory apparatus of claim 13 , wherein the controller is configured to:

sample the first voltage of the second access line at the first node;

isolate the first node after sampling the first voltage;

sample the second voltage of the first access line at the second node after isolating the first node; and

isolate the second node after sampling the second voltage.

15. The electronic memory apparatus of claim 14 wherein the ferroelectric memory cell has a residual polarization after sampling the first voltage.

16. The electronic memory apparatus of claim 10 , wherein the controller is configured to:

write the logic value to the ferroelectric memory cell after a comparison of the first voltage and the second voltage.