Memory array with multiplexed digit lines
Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
1 . A memory device, comprising:
a memory cell coupled with a digit line and a plate line, the memory cell comprising a storage component, a first transistor coupled with the storage component and the digit line, and a second transistor coupled with the storage component and the plate line;
a word line coupled with a gate of the first transistor and configured to selectively couple the storage component with the digit line;
a select line coupled with a gate of the second transistor and configured to selectively couple the storage component with the plate line;
a sense component configured to selectively couple with a plurality of digit lines comprising the digit line; and
a third transistor coupled with the select line and configured to selectively couple the digit line with the sense component during at least a portion of a read operation.
2 . The memory device of claim 1 , further comprising:
a second memory cell coupled with the word line and a second digit line of the plurality; and
a fourth transistor configured to selectively couple the second digit line of the plurality with the sense component, a gate of the fourth transistor coupled with a second select line.
3 . The memory device of claim 1 , wherein:
the first transistor is a first vertical transistor that comprises a first doped region that extends in a first direction between the storage component and the digit line; and
the second transistor is a second vertical transistor that comprises a second doped region that extends in the first direction between the storage component and the plate line.
4 . The memory device of claim 3 , wherein:
the first doped region is positioned between the second doped region and a substrate of the memory device in the first direction.
5 . The memory device of claim 4 , wherein the storage component is positioned between the first doped region and the second doped region in the first direction.
6 . A memory device, comprising:
a memory cell coupled with a digit line and a plate line, the memory cell comprising a storage component and two transistors connected in a series configuration;
a word line coupled with a gate of a first transistor of the two transistors and configured to select the memory cell;
a select line coupled with a gate of a second transistor of the two transistors and configured to couple the memory cell with the digit line;
a sense component configured to selectively couple with a plurality of digit lines comprising the digit line; and
a third transistor coupled with the select line and configured to selectively couple the digit line with the sense component during at least a portion of a read operation.
7 . The memory device of claim 6 , wherein a first node of at least one of the two transistors is coupled with the storage component and a second node of another of the two transistors is coupled with the digit line.
8 . The memory device of claim 7 , wherein the first transistor is coupled with the storage component at the first node and the second transistor is coupled with the digit line at the second node.
9 . The memory device of claim 7 , wherein the first transistor is coupled with the digit line at the second node and the second transistor is coupled with the storage component at the first node.
10 . The memory device of claim 6 , further comprising:
a second memory cell coupled with the word line and a second digit line of the plurality; and
a fourth transistor configured to selectively couple the second digit line of the plurality with the sense component, a gate of the fourth transistor coupled with a second select line.
11 . The memory device of claim 6 , wherein:
the first transistor is a first vertical transistor that comprises a first doped region that extends in a first direction between the storage component and the digit line; and
the second transistor is a second vertical transistor that comprises a second doped region that extends in the first direction between the storage component and the plate line.
12 . The memory device of claim 11 , the first doped region is positioned between the second doped region and a substrate of the memory device in the first direction.
13 . The memory device of claim 6 , wherein the storage component is coupled with the plate line.
14 . The memory device of claim 6 , wherein the memory cell comprises a dynamic random access memory (DRAM) cell.
15 . A memory device, comprising:
a memory cell comprising a storage component, a first transistor, and a second transistor, wherein the first transistor and the second transistor are coupled with the storage component;
a word line coupled with the memory cell;
a digit line coupled with the first transistor of the memory cell and extending in a first direction;
a select line coupled with the second transistor of the memory cell, the select line configured to selectively couple the memory cell with the digit line;
a sense component configured to be selectively coupled with a plurality of digit lines that comprise the digit line; and
a third transistor configured to selectively couple the digit line with the sense component, a gate of the third transistor coupled with the select line.
16 . The memory device of claim 15 , further comprising:
a second memory cell coupled with the word line and a second digit line of the plurality; and
a fourth transistor configured to selectively couple the second digit line of the plurality with the sense component, a gate of the fourth transistor coupled with a second select line.
17 . The memory device of claim 15 , wherein the word line extends in a second direction orthogonal to the first direction.
18 . The memory device of claim 17 , wherein the first direction and the second direction are parallel to a surface of a substrate.