Memory cell and memory array utilizing the memory cell
A memory cell comprising a first switch device, a second switch device and a capacitor is disclosed. The first switch device has: a control terminal coupled to a select line, wherein the first switch device is controlled by the select line; a first terminal, coupled to a bit line parallel with the select line. The second switch device has: a first terminal, coupled to the second terminal of the first switch device; a control terminal, coupled to a word line orthogonal to the bit line and the select line, wherein the second switch device is controlled by the word line. The capacitor has a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein the data is read from the capacitor or written to the capacitor via the bit line.
1. A memory cell, comprising:
a first switch device, having:
a control terminal coupled to a select line, wherein the first switch device is controlled by the select line to be turned on or turned off;
a first terminal, coupled to a bit line parallel with the select line; and
a second terminal;
a second switch device, having:
a first terminal, coupled to the second terminal of the first switch device;
a control terminal, coupled to a word line orthogonal to the bit line and the select line, wherein the second switch device is controlled by the word line to be turned on or turned off; and
a second terminal; and
a capacitor, having a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein the data is read from the capacitor or written to the capacitor via the bit line.
2. The memory cell of claim 1 , wherein the second terminal of the first switch device is directly connected to the first terminal of the second switch device.
3. The memory cell of claim 1 , wherein the first switch device and the second switch device are NMOSFETs, where the first terminals of the first switch device and the second switch device are drain terminals, the control terminals of the first switch device and the second switch device are gate terminals, and the second terminals of the first switch device and the second switch device are source terminals.
4. The memory cell of claim 1 , wherein the first switch device and the second switch device are PMOSFETs, where the first terminals of the first switch device and the second switch device are source terminals, the control terminals of the first switch device and the second switch device are gate terminals, and the second terminals of the first switch device and the second switch device are drain terminals.
5. A memory array, comprising:
a plurality of memory cells, wherein each of the memory cells comprises:
a first switch device, having:
a control terminal coupled to a column select line, wherein the first switch device is controlled by the column select line to be turned on or turned off;
a first terminal, coupled to a bit line parallel with the column select line; and
a second terminal;
a second switch device, having:
a first terminal, coupled to the second terminal of the first switch device;
a control terminal coupled to a word line orthogonal to the bit line and the column select line, wherein the second switch device is controlled by the word line to be turned on or turned off; and
a second terminal; and
a capacitor, having a first terminal coupled to the second terminal of the second switch device and a second terminal coupled to a predetermined voltage level, wherein the data is read from the capacitor or written to the capacitor via the bit line.
6. The memory array of claim 5 , wherein the memory cells in the memory array can be classified into multiple groups of memory cells, and the bit lines of the memory array are arranged in a way that no adjacent bit lines are from the same group of memory cells, when the bit lines of one of the multiple groups of memory cells are transmitting data, the bit lines of the other groups of memory cells are not transmitting data.
7. The memory array of claim 5 , wherein the second terminal of the first switch device is directly connected to the first terminal of the second switch device.
8. The memory array of claim 5 , wherein the first switch device and the second switch device are NMOSFETs, where the first terminals of the first switch device and the second switch device are drain terminals, the control terminals of the first switch device and the second switch are gate terminals, and the second terminals of the first switch device and the second switch device are source terminals.
9. The memory array of claim 5 , wherein the first switch device and the second switch device are PMOSFETs, where the first terminals of the first switch device and the second switch device are source terminals, the control terminals of the first switch device and the second switch are gate terminals, and the second terminals of the first switch device and the second switch device are drain terminals.
10. The memory array of claim 5 , wherein the memory cell is provided at each intersection of the bit lines and the word lines.