Memory array with multiplexed digit lines
Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
1. A method, comprising:
activating a first transistor of a memory cell coupled with a word line;
activating a second transistor of the memory cell coupled with a select line;
coupling, by a third transistor coupled with the select line, a digit line with a sense component configured to selectively couple with a plurality of digit lines comprising the digit line; and
determining, by the sense component, a logic state stored in a storage component of the memory cell based at least in part on activating the first transistor, activating the second transistor, and coupling the digit line with the sense component.
2. The method of claim 1 , further comprising:
biasing the select line to a voltage, wherein activating the second transistor of the memory cell and coupling the digit line with the sense component are based at least in part on biasing the select line to the voltage.
3. The method of claim 2 , further comprising:
biasing the word line to a second voltage, wherein activating the first transistor of the memory cell and coupling the digit line with the sense component are based at least in part on biasing the word line to the second voltage.
4. The method of claim 3 , wherein the select line is biased before the word line is biased.
5. The method of claim 3 , wherein the select line is biased at the same time or after the word line is biased.
6. The method of claim 1 , further comprising:
coupling a second digit line of the plurality of digit lines with a plate line, wherein coupling the digit line with the sense component is based at least in part on coupling the second digit line of the plurality of digit lines with the plate line.
7. The method of claim 1 , further comprising:
causing a second digit line of the plurality of digit lines to float, wherein coupling the digit line with the sense component is based at least in part on causing the second digit line of the plurality of digit lines to float.
8. The method of claim 1 , further comprising:
outputting the logic state stored in the storage component of the memory cell based at least in part on determining the logic state by the sense component.
9. The method of claim 1 , further comprising:
receiving a command comprising an instruction to perform a read operation on the memory cell, wherein activating the first transistor and the second transistor of the memory cell are based at least in part on receiving the command.
10. A method, comprising:
activating a first transistor of a memory cell coupled with a word line;
activating a second transistor of the memory cell coupled with a select line;
coupling, by a third transistor coupled with the select line, a digit line with a sense component configured to selectively couple with a plurality of digit lines comprising the digit line; and
determining, by the sense component, a logic state stored in a storage component of the memory cell based at least in part on activating the first transistor, activating the second transistor, and coupling the digit line with the sense component;
receiving a command comprising an instruction to perform a read operation on the memory cell, wherein activating the first transistor and the second transistor of the memory cell are based at least in part on receiving the command;
receiving a second command comprising an instruction to perform a second read operation on a second memory cell coupled with the sense component through a second digit line of the plurality of digit lines;
decoupling, by the third transistor, the digit line from the sense component based at least in part on receiving the second command; and
coupling, by a fourth transistor coupled with a second select line, the second digit line of the plurality of digit lines with the sense component, based at least in part on decoupling the digit line from the sense component.
11. The method of claim 10 , further comprising:
outputting a logic state stored in the second memory cell based at least in part on coupling the second digit line of the plurality of digit lines with the sense component.