Patent Assignment
Reel/Frame 048948/0677
Supplement No. 12 to Patent Security Agreement
Recorded: 2019-04-19
Pages: 68
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2019-04-16
Assignee
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
1300 THAMES STREET, 4TH FLOOR, BALTIMORE, MARYLAND, 21231
Covered Properties
(925)
Preemptive Idle Time Read Scans
Volatile Memory Device with 3-D Structure Including Vertical Pillars and Memory Cells Vertically Stacked One Over Another in Multiple Levels
Capacitive Voltage Modifier for Power Management
Patent:
10,482,979 →
Application:
16/119,715 →
Reduced Peak Self-Refresh Current in a Memory Device
Apparatus Having a Data Receiver with a Real Time Clock Decoding Decision Feedback Equalizer
Memory Device Architecture
Memory Device Architecture
Apparatuses and Methods for Providing an Indicator of Operational Readiness of Various Circuits of a Semiconductor Device Following Power Up
Stack Access Control for Memory Device
Key Management in Computer Processors
Multifunctional Memory Cells
Apparatuses and Methods for Plate Coupled Sense Amplifiers
Wavelength Converters, Including Polarization-Enhanced Carrier Capture Converters, for Solid State Lighting Devices, and Associated Systems and Methods
Memory Components with Ordered Sweep Error Recovery
Row Hammer Refresh for Content Addressable Memory Devices
Dll Circuit Having Variable Clock Divider
Apparatuses and Methods for Controlling Data Timing in a Multi-Memory System
Methods and Apparatuses for Executing a Plurality of Queued Tasks in a Memory
Reversed Bias Compensation for Sense Amplifier Operation
Patent:
10,482,931 →
Application:
16/137,175 →
Interconnections for 3D Memory
Apparatuses and Methods Including Memory and Operation of Same
Semiconductor Devices with Post-Probe Configurability
Methods of Fluxless Micro-Piercing of Solder Balls, and Resulting Devices
Temperature Informed Memory Refresh
Photonics Grating Coupler and Method of Manufacture
Apparatuses and Methods for Reading Memory Cells
Data Transfer Between Subarrays in Memory
Adjusting Scan Event Thresholds to Mitigate Memory Errors
Memory Device with Improved Writing Features
Apparatuses for Selective Tsv Block Testing
Frequency Synthesis for Memory Input-Output Operations
Memory Cells Programmed via Multi-Mechanism Charge Transports
3D Interconnect Multi-Die Inductors with Through-Substrate via Cores
Scrubber Driven Wear Leveling in Out of Place Media Translation
Semiconductor Device with a Data-Recording Mechanism
Data Transfer in Port Switch Memory
Addressing in Memory with a Read Identification (Rid) Number
Integrated Circuitry Comprising An Array, Method Of Forming An Array, Method Of Forming DRAM Circuitry, And Method Used In The Fabrication Of Integrated Circuitry
Direct Data Transfer in Memory and Between Devices of a Memory Module
Apparatus and Methods for Debugging on a Memory Device
Host-Resident Translation Layer Validity Check Techniques
Configurable Buffer Manager Arbitration Request Throttling Mechanism
Configurable Burst Optimization for a Parameterizable Buffer
Isolation Component
Methods and Apparatuses for Error Correction
Wirelessly Utilizable Memory
Remotely Executable Instructions
Memory Pooling Between Selected Memory Resources
Memory Pooling Between Selected Memory Resources via a Base Station
Memory Pooling Between Selected Memory Resources on Vehicles or Base Stations
Accessing a Memory Resource at One or More Physically Remote Entities
Sharing a Memory Resource Among Physically Remote Entities
Data Center Using a Memory Pool Between Selected Memory Resources
Charge Pump Supply Optimization and Noise Reduction Method for Logic Systems
Apparatuses and Methods for Protecting Transistor in a Memory Circuit
Apparatuses and Methods for Drivers with Reduced Noise
Patent:
10,522,208 →
Application:
16/144,693 →
Apparatuses and Methods for Providing a Signal with a Differential Phase Mixer
Apparatuses and Methods for Internal Voltage Generating Circuits
Zone Based Reconstruction of Logical to Physical Address Translation Map
Apparatuses and Methods for Providing Reference Voltages
Integrated Circuitry, DRAM Circuitry, Method Of Forming A Plurality Of Conductive Vias, And Method Of Forming DRAM Circuitry
Data Erasure in Memory Sub-Systems
Apparatuses and Methods for Comparing a Current Representative of a Number of Failing Memory Cells
Memory Devices Having Selectively Electrically Connected Data Lines
Access Unit and Management Segment Memory Operations
Copy-Back Operations in a Memory Device
Semiconductor Layered Device with Data Bus
Reducing Data Hazards in Pipelined Processors to Provide High Processor Utilization
Systems and Methods for Improved Reliability of Components in Dynamic Random Access Memory (Dram)
Buffer Circuit
Patent:
10,389,359 →
Application:
16/151,274 →
Apparatus with a Calibration Mechanism
Patent:
10,504,571 →
Application:
16/151,604 →
Caul Plates and Related Methods
Performing Hybrid Wear Leveling Operations Based on a Sub-Total Write Counter
Apparatus Having Multiplexers for Passive Input/Output Expansion and Methods of Their Operation
Methods of Forming Semiconductor Devices Using Mask Materials, and Related Semiconductor Devices and Systems
Stacked Semiconductor Die Assemblies with Die Substrate Extensions
Real Time Trigger Rate Monitoring in a Memory Sub-System
Elevationally-Extending Transistors, Devices Comprising Elevationally-Extending Transistors, and Methods of Forming a Device Comprising Elevationally-Extending Transistors
Quadrature Signal Generation
Patent:
10,476,660 →
Application:
16/155,512 →
Multiple Memory Devices Having Parity Protection
Sacrificial Separators for Wafer Level Encapsulating
Three-Dimensional Memory Array
Patent:
10,593,730 →
Application:
16/156,194 →
Memory Cell Sensing Based on Precharging an Access Line Using a Sense Amplifier
Patent:
10,546,629 →
Application:
16/156,347 →
Counter-Based Compaction of Key-Value Store Tree Data Block
Key-Value Store Tree Data Block Spill with Compaction
Coherent Memory Access
Vector Registers Implemented in Memory
Apparatuses and Methods for Providing Voltages to Conductive Lines Between Which Clock Signal Lines Are Disposed
Patent:
10,418,081 →
Application:
16/156,862 →
Dynamic Background Scan Optimization in a Memory Sub-System
Unretiring Memory Device Blocks
Nand Parity Information Techniques for Systems with Limited Ram
Data Transfer for Wear Leveling with Bank Clusters
Reactive Read Based on Metrics to Screen Defect Prone Memory Blocks
Methods and Apparatuses Including a Boundary of a Well Beneath an Active Area of a Tap
Forming Terminations in Stacked Memory Arrays
Dielectric Extensions in Stacked Memory Arrays
Formation of Termination Structures in Stacked Memory Arrays
Termination Structures in Stacked Memory Arrays
Methods for Determining an Expected Data Age of Memory Cells
Apparatus and Methods for Determining an Expected Data Age of Memory Cells
Patent:
10,553,289 →
Application:
16/161,256 →
Memory Device Processing
Patent:
10,483,978 →
Application:
16/161,825 →
Intelligent Post-Packaging Repair
Methods for Forming Interconnect Assemblies with Probed Bond Pads
Auto-Zero Technique for Opamps with a Source-Follower Output Stage Based on Replica Referencing
Semiconductor Device Performing Refresh Operation in Deep Sleep Mode
Semiconductor Device with First-in-First-Out Circuit
Power Noise Reduction Technique for High Density Memory with Gating
Patent:
10,403,330 →
Application:
16/163,720 →
Power Noise Reduction Technique for High Density Memory with Frequency Adjustments
Patent:
10,418,073 →
Application:
16/163,728 →
Memory for Embedded Applications
Modifying Memory Bank Operating Parameters
Patent:
10,600,496 →
Application:
16/164,156 →
Mitigating an Undetectable Error When Retrieving Critical Data During Error Handling
Passivation Material for a Pillar Adjacent a Trench
Vertical Solid-State Transducers and High Voltage Solid-State Transducers Having Buried Contacts and Associated Systems and Methods
Semiconductor Devices Having Integrated Optical Components
Event Counters for Memory Operations
Selectively Controlling Clock Transmission to a Data (Dq) System
Construction Of Integrated Circuitry And A Method Of Forming An Elevationally-Elongated Conductive Via To A Diffusion Region In Semiconductive Material
Dynamic Temperature Compensation in a Memory Component
Data-Structure Based Dynamic Program Targeting Control
Data Replication
Two-Stage Hybrid Memory Buffer for Multiple Streams
Write Atomicity Management for Memory Subsystems
Write Training in Memory Devices
Multi-Port Storage-Class Memory Interface
Semiconductor Devices Including a Stair Step Structure, and Related Methods
Semiconductor Packages Having Photon Integrated Circuit (Pic) Chips
Semiconductor Devices Having Electro-Optical Substrates
Dynamic Delay of Nand Read Commands
Periodic Flush in Memory Component That Is Using Greedy Garbage Collection
Error-Checking in Namespaces on Storage Devices Using a Namespace Table and Metadata
Power-On-Time Based Data Relocation
Relocating Data to Low Latency Memory
Read Disturb Scan Consolidation
Patent:
10,553,290 →
Application:
16/175,657 →
Vectorized Processing Level Calibration in a Memory Component
Sensing Charge Recycling Circuitry
Apparatuses and Methods for Access Based Refresh Timing
Shared Error Check and Correct Logic for Multiple Data Banks
Implementing Sticky Read Using Error Control Success Rate Associated with a Memory Sub-System
Performing an on Demand Refresh Operation of a Memory Sub-System
Data Relocation in Memory
Charge Pump Supply Oscillator
Data Programming
Offset Cancellation of Duty Cycle Detector
Patent:
10,601,410 →
Application:
16/179,349 →
Memory Array And A Method Used In Forming A Memory Array
Apparatus with a Row Hit Rate/Refresh Management Mechanism
Patent:
10,504,577 →
Application:
16/181,117 →
Dedicated Read Voltages for Data Structures
Memory Element Profiling and Operational Adjustments
Semiconductor Devices Having Electrically and Optically Conductive Vias, and Associated Systems and Methods
Interconnect Structures for Preventing Solder Bridging, and Associated Systems and Methods
Semiconductor Devices Having 3-Dimensional Inductive Structures
Optimization of Data Access and Communication in Memory Systems
Sequential Voltage Ramp-Down of Access Lines of Non-Volatile Memory Device
Apparatuses Including Threshold Voltage Compensated Sense Amplifiers and Methods for Compensating Same
Patent:
10,586,586 →
Application:
16/183,594 →
Client-Assisted Phase-Based Media Scrubbing
Reduce Data Traffic between Cache and Memory via Data Access of Variable Sizes
Methods for Forming Narrow Vertical Pillars and Integrated Circuit Devices Having the Same
Sensing and Tuning for Memory Die Power Management
Apparatus and Methods for Discharging Control Gates After Performing an Access Operation on a Memory Cell
High-Reliability Non-Volatile Memory Using a Voting Mechanism
Storing Parity Data Mid Stripe
Apparatuses and Methods for Targeted Refreshing of Memory
Packaged Microelectronic Devices and Methods for Manufacturing Packaged Microelectronic Devices
Logical Block Mapping Based on an Offset
Apparatuses and Method for Reducing Row Address to Column Address Delay
Address Obfuscation for Memory
Invert Operations Using Sensing Circuitry
Memory Arrays Comprising Memory Cells
Temperature Correction in Memory Sub-Systems
Read Retry with Targeted Auto Read Calibrate
Systems, Devices, Techniques, and Methods for Data Migration
Systems, Devices, and Methods for Data Migration
Data Migration for Memory Operation
Data Migration Dynamic Random Access Memory
Scan Frequency Modulation Based on Memory Density or Block Usage
Memory Sub-System for Performing Wear-Leveling Adjustments Based on Memory Component Endurance Estimations
Methods and Apparatuses for Independent Tuning of on-Die Termination Impedances and Output Driver Impedances, and Related Semiconductor Devices and Systems
Patent:
10,585,835 →
Application:
16/196,545 →
Error Correction Bit Flipping Scheme
Memory Arrays and Methods Used in Forming a Memory Array
Write Width Aligned Storage Device Buffer Flush
Apparatus and Methods for Managing Data Storage Among Groups of Memory Cells of Multiple Reliability Ranks
Systems for Generating Process, Voltage, Temperature (Pvt)-Independent Current
Patent:
10,331,151 →
Application:
16/203,320 →
Memory Arrays And Methods Used In Forming A Memory Array
Techniques Using Nonvolatile Memory and Volatile Memory
Memory Disablement for Data Security
Wear Leveling for Non-Volatile Memory Using Data Write Counters
Memory Arrays
Heat Spreaders for Semiconductor Devices, and Associated Systems and Methods
Reduction of Zq Calibration Time
Patent:
10,529,390 →
Application:
16/205,450 →
Apparatus and Methods for Serializing Data Output
Leakage Current Reduction in Electronic Devices
Refresh Command Management
Per Cursor Logical Unit Number Sequencing
Vertical Decoder
Patent:
10,559,337 →
Application:
16/206,006 →
Responding to Power Loss
Patent:
10,607,702 →
Application:
16/207,341 →
Semiconductor Pitch Patterning
Integrated Assemblies Which Include Metal-Containing Interconnects to Active-Region Pillars, and Methods of Forming Integrated Assemblies
Methods of Forming Sublithographic Features of a Semiconductor Device
Application:
16/208,122 →
Publication:
US US20200176255A1
Enhanced Flush Transfer Efficiency via Flush Prediction
Patent:
10,573,391 →
Application:
16/208,165 →
Processing in Memory
Estimating the Temperature of a Memory Sub-System
Managing Redundancy Contexts in Storage Devices Using Eviction and Restoration
Selective Relocation of Data of a Subset of a Data Block Based on Distribution of Reliability Statistics
Performing a Test of Memory Components with Fault Tolerance
Allocation of Test Resources to Perform a Test of Memory Components
Asymmetric Source/Drain Regions of Transistors
Processors with Security Levels Adjustable per Applications
Protection Against Timing-Based Security Attacks By Randomly Adjusting Reorder Buffer Capacity
Nand Device Mixed Parity Management
Methods and Apparatus for Incentivizing Participation in Fog Networks
Direct-Input Redundancy Scheme with Dedicated Error Correction Code Circuit
Direct-Input Redundancy Scheme with Adaptive Syndrome Decoder
Memory Circuitry And Methods Of Forming Memory Circuitry
Memory Circuit Package with Adjustable Active Channel Count
Application:
16/213,720 →
Publication:
US US20200183622A1
Memory Devices with Controlled Wordline Ramp Rates, and Associated Systems and Methods
Patent:
10,546,641 →
Application:
16/214,007 →
Read Window Budget Based Dynamic Program Step Characteristic Adjustment
Level Width Based Dynamic Program Step Characteristic Adjustment
Adjusting Program Effective Time Using Program Step Characteristics
Trigger Margin Based Dynamic Program Step Characteristic Adjustment
Bit Error Rate Based Dynamic Program Step Characteristic Adjustment
Apparatuses and Methods for Performing Corner Turn Operations Using Sensing Circuitry
Management of Corruptive Read in Memory Systems
Defect Detection in Memories with Time-Varying Bit Error Rate
Semiconductor Devices and Electronic Systems Including an Etch Stop Material, and Related Methods
Memory Data Security
Phase Charge Sharing Reduction
Dual Thermoelectric Component Apparatus with Thermal Transfer Component
Application:
16/218,029 →
Publication:
US US20200194650A1
Thermal Chamber for a Thermal Control Component
Multiple Algorithmic Pattern Generator Testing of a Memory Device
3D Stacked Integrated Circuits Having Failure Management
3D Stacked Integrated Circuits Having Functional Blocks Configured to Provide Redundancy Sites
Host Clock Effective Delay Range Extension
Automated Power Down Based on State of Firmware
Controller Structural Testing with Automated Test Vectors
Mapping Table Compression Using a Run Length Encoding Algorithm
Key-Value Store Using Journaling with Selective Data Storage Format
Key-Value Store Tree with Selective Use of Key Portion
Refresh-Related Activation in Memory
Methods for Determining Data States of Memory Cells
Low-Voltage Bias Generator Based on High-Voltage Supply
Patent:
10,539,973 →
Application:
16/221,987 →
Stage Protection in Multi-Stage Charge Pumps
Management of Test Resources to Perform Reliability Testing of Memory Components
Multi-Dimensional Usage Space Testing of Memory Components
Selective Compression Circuitry in a Memory Device
Apparatuses and Methods for Storing and Writing Multiple Parameter Codes for Memory Operating Parameters
Handling Operation Collisions in a Non-Volatile Memory
Patent:
10,521,383 →
Application:
16/223,057 →
Apparatus and Methods for Programming Memory Cells Using Multi-Step Programming Pulses
Apparatuses, Memory Devices, and Electronic Systems
Thin Film Transistors and Related Fabrication Techniques
Memory Array Decoding and Interconnects
Data Storage Organization Based on One or More Stresses
Seed Operation for Memory Devices
Patent:
10,643,706 →
Application:
16/224,901 →
Memory Module Interfaces
Array Of Capacitors, Array Of Memory Cells, Methods Of Forming An Array Of Capacitors, And Methods Of Forming An Array Of Memory Cells
Memory Module Including a Controller and Interfaces for Communicating with a Host and Another Memory Module
Host-Resident Translation Layer Validity Check Techniques
Module Processing Resource
Application:
16/226,119 →
Publication:
US US20200201566A1
Predictive Data Storage Hierarchical Memory Systems and Methods
Generating a Random Value Based on a Noise Characteristic of a Memory Cell
Reading Even Data Lines or Odd Data Lines Coupled to Memory Cell Strings
Integrated-Circuitry Overlay Alignment Mark, A Substrate Comprising An Overlay Alignment Mark, A Method Of Forming An Overlay Alignment Mark In The Fabrication Of Integrated Circuitry, And A Method Of Determining Overlay Alignment In The Fabrication Of Integrated Circuitry
Power Loss Test Engine Device and Method
Methods and Apparatuses for Threshold Voltage Measurement and Related Semiconductor Devices and Systems
Dynamic Memory Programming Voltage Step for Strenuous Device Conditions
Exception Handling Based on Responses to Memory Requests in a Memory Subsystem
Application:
16/228,460 →
Publication:
US US20200201568A1
Chalcogenide Memory Device Components and Composition
Programming Multiple-Level Memory Cells with Multiple-Pass
Three-Dimensional Memory Array
Host-Based Flash Memory Maintenance Techniques
Flash Memory Persistent Cache Techniques
Memory Security Techniques Using Auto Refresh Validation
Patent:
10,665,290 →
Application:
16/230,573 →
Apparatuses and Methods for Ordering Bits in a Memory Device
Apparatuses and Methods for Organizing Data in a Memory Device
Scan Optimization from Stacking Multiple Reliability Specifications
Sensing Techniques Using a Charge Transfer Device
Sensing Techniques Using a Charge Transfer Device
Write Techniques for a Memory Device with a Charge Transfer Device
Sensing Techniques Using Charge Transfer Device
Patent:
10,665,292 →
Application:
16/232,303 →
Sensing Techniques Using a Moving Reference
Techniques for Charging a Sense Component
Memory Device with a Charge Transfer Device
Tuning Voltages in a Read Circuit
Patent:
10,650,888 →
Application:
16/232,359 →
Data Tree with Order-Based Node Traversal
Sensing Architecture
Methods and Systems for Measuring Semiconductor Devices
Semiconductor Packages and Associated Methods with Solder Mask Opening(S) for in-Package Ground and Conformal Coating Contact
Read Window Size
Garbage Collection Candidate Selection Using Block Overwrite Rate
Foreign Material Cleaning System for Compression Molding
Apparatus with a Current-Gain Layout
Apparatus with a Row-Hammer Address Latch Mechanism
Memory Management Utilzing Buffer Reset Commands
Host Inquiry Response Generation in a Memory Device
Variable Read Error Code Correction
Replay Protection Nonce Generation
Unauthorized Memory Access Mitigation
Disposable Parity
Silicon Doping for Laser Splash Blockage
Non-Persistent Unlock for Secure Memory
Unauthorized Access Command Logging Using a Key for a Protected Region of Memory
Host Adaptive Memory Device Optimization
Memory Device Error Detection with Improved Scanning
Methods of Forming Tungsten Structures
Accelerated Memory Device Trim Initialization
Application:
16/235,925 →
Publication:
US US20200210105A1
Adjustable Nand Write Performance
Extended Error Correction in Storage Device
Semiconductor Devices Having Crack-Inhibiting Structures
Semiconductor Devices Having Crack-Inhibiting Structures
Computing Tile
Patent:
10,606,775 →
Application:
16/236,188 →
Methods and Systems for Manufacturing Pillar Structures on Semiconductor Devices
Methods and Systems for Manufacturing Semiconductor Devices
Methods and Systems for Manufacturing Semiconductor Devices
Methods and Systems for Manufacturing Semiconductor Devices
Bond Chucks Having Individually-Controllable Regions, and Associated Systems and Methods
Bond Chucks Having Individually-Controllable Regions, and Associated Systems and Methods
Systems for Providing Access to Protected Memory
Memory Device Policy Enforcement Using Firmware
Application:
16/236,876 →
Publication:
US US20200210106A1
Memory with Partial Array Refresh
Configurable Nand Firmware Search Parameters
Systems and Methods for Forming Semiconductor Cutting/Trimming Blades
Package Cooling by Coil Cavity
Memory with on-Die Data Transfer
Error Correction in Row Hammer Mitigation and Target Row Refresh
Normalization of Detecting and Reporting Failures for a Memory Device
Patterned Carrier Wafers and Methods of Making and Using the Same
Apparatus and Methods for Refreshing Memory
Structure and Methods of Forming the Structure
Configurable Post-Package Repair
Phase Change Memory Stack with Treated Sidewalls
Methods and Apparatus for Routine Based Fog Networking
Semiconductor Device Assemblies with Molded Support Substrates
Stopping Criteria for Layered Iterative Error Correction
Updating Reliability Data
Memory Read Apparatus and Methods
Methods and Systems for Devices with Self-Selecting Bus Decoder
Systems and Methods for Improving Power Efficiency in Refreshing Memory Banks
Semiconductor Device Assembly with Vapor Chamber
Method and Structure Providing Optical Isolation of a Waveguide on a Silicon-on-Insulator Substrate
Driver Placement in Memories Having Stacked Memory Arrays
Systems and Methods for Wafer Alignment
Integrated Assemblies Having Spacers of Low Permittivity Along Digit-Lines, and Methods of Forming Integrated Assemblies
Patent:
10,546,862 →
Application:
16/248,584 →
Memory System and Operations of the Same
Devices Comprising a Capacitor and Support Material That Laterally Supports the Capacitor
Buses for Pattern-Recognition Processors
Apparatuses and Methods for Decoding Addresses for Memory
Code Word Format and Structure
Forwading Code Word Address
Methods of Forming an Apparatus for Making Semiconductor Devices
Apparatus with Multidielectric Spacers on Conductive Regions of Stack Structures, and Related Methods
Conductive Line Construction, Memory Circuitry, and Method of Forming a Conductive Line Construction
Memory Arrays And Methods Used In Forming A Memory Array
Methods for Phase-Change Memory Array
Cell Pillar Structures and Integrated Flows
Vertical Decoders
Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry
Techniques for Read Operations
Memory Devices with Cryptographic Components
Methods of Forming Patterns, and Methods of Patterning Conductive Structures of Integrated Assemblies
Patent:
10,636,658 →
Application:
16/255,458 →
Slit Oxide and via Formation Techniques
Compensating for Memory Input Capacitance
Apparatuses and Methods for Soft Post-Package Repair
Methods of Doping a Silicon-Containing Material and Methods of Forming a Semiconductor Device
Interconnect Structure with Redundant Electrical Connectors and Associated Systems and Methods
Polarity-Written Cell Architectures for a Memory Device
Semiconductor Mold Compound Transfer System and Associated Methods
Timing Control Circuit Shared by a Plurality of Banks
Semiconductor Devices Comprising Digit Line Contacts and Related Systems
Formation of a Capacitor Using a Sacrificial Layer
Column Formation Using Sacrificial Material
Reduction of Roughness on a Sidewall of an Opening
Semiconductor Structure Formation
Apparatuses and Methods for Detection Refresh Starvation of a Memory
Formation of a Capacitor Using a Hard Mask
Contact Patterning
High-Voltage Shifter with Degradation Compensation
Formation of a Trench Using a Polymerizing Radical Material
Application:
16/259,634 →
Publication:
US US20200243537A1
High-Voltage Shifter with Reduced Transistor Degradation
Patent:
10,586,600 →
Application:
16/259,671 →
Memory Controller with Programmable Atomic Operations
Power Management Component for Memory Sub-System Voltage Regulation
Error Detection Code Hold Pattern Synchronization
Semiconductor Device Having Equivalent Series Resistance Unit
Pads for Chemical Mechanical Planarization Tools, Chemical Mechanical Planarization Tools, and Related Methods
Apparatuses and Methods for Cache Invalidate
Metadata-Assisted Encoding and Decoding for a Memory Sub-System
Early Decoding Termination for a Memory Sub-System
Interface for Data Communication Between Chiplets or other Integrated Circuits on an Interposer
Phase Change Memory Stack with Treated Sidewalls
Memory Arrays, and Methods of Forming Memory Arrays
High Bandwidth Memory Having Plural Channels
Apparatus and Methods for Determining Data States of Memory Cells
Multi-Page Parity Protection with Power Loss Handling
Dynamic Allocation of a Capacitive Component in a Memory Device
Solid State Optoelectronic Device with Preformed Metal Support Substrate
Apparatuses and Methods for Managing Row Access Counts
Semiconductor Device Structures for Burn-in Testing and Methods Thereof
Power Reduction for a Sensing Operation of a Memory Cell
Formation of an Atomic Layer of Germanium in an Opening of a Substrate Material Having a High Aspect Ratio
Reduction of Crystal Growth Resulting from Annealing a Conductive Material
Methods of Memory Address Verification and Memory Devices Employing the Same
Apparatus and Method for Controlling Erasing Data in Ferroelectric Memory Cells
Arrays Of Memory Cells Individually Comprising A Capacitor And A Transistor And Methods Of Forming Such Arrays
Two-Step Data-Line Precharge Scheme
Use of Pre-Channeled Materials for Anisotropic Conductors
Atom Implantation for Passivation of Pillar Material
Methods and Apparatuses for Compensating for Source Voltage
Integrated Circuitry And 3D Memory
Powering Clock Tree Circuitry Using Internal Voltages
Apparatuses and Methods for Semiconductor Die Heat Dissipation
Memory Cells, Magnetic Memory Cells, and Semiconductor Devices
Methods of Forming an Array of Elevationally-Extending Strings of Memory Cells
Method of Forming A Semiconductor Device Including A Pitch Multiplication
Apparatuses and Methods for Providing Data to a Configurable Storage Area
Methods and Apparatuses Including a Process, Voltage, and Temperature Independent Current Generator Circuit
Input Buffer Circuit
Apparatuses and Methods for Providing Active and Inactive Clock Signals
Discontinuous Patterned Bonds for Semiconductor Devices and Associated Systems and Methods
Apparatuses and Methods for Configurable Command and Data Input Circuits for Semiconductor Memories
Methods of Forming Alignment Marks During Patterning of Semiconductor Material
Patent:
10,651,129 →
Application:
16/273,733 →
Apparatuses and Methods for Generating a Voltage in a Memory
Test Access Port Architecture to Facilitate Multiple Testing Modes
Charge Loss Failure Mitigation
Apparatuses and Methods for Duty Cycle Distortion Correction of Clocks
Shielded Vertically Stacked Data Line Architecture for Memory
Gate Electrode Layout with Expanded Portions Over Active and Isolation Regions
Solid State Lighting Systems and Associated Methods of Operation and Manufacture
Methods and Apparatus for Characterizing Memory Devices
Methods and Apparatus for Checking the Results of Characterized Memory Searches
Apparatuses Including Input Buffers and Methods for Operating Input Buffers
Methods and Apparatus for Maintaining Characterized Memory Devices
Semiconductor Devices Having Discretely Located Passivation Material, and Associated Systems and Methods
Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry
Memory Arrays and Methods Used in Forming a Memory Array
Apparatuses Having Body Connection Lines Coupled with Access Devices
Error Correction on a Memory Device
Apparatuses and Methods of Reading Memory Cells
Flexible Memory System with a Controller and a Stack of Memory
Component Inter-Digitated Vias and Leads
Memory Sub-System for Supporting Deterministic and Non-Deterministic Commands Based on Command Expiration and the State of the Intermediate Command Queue
Adaptive Content Inspection
Application:
16/280,872 →
Publication:
US US20190180191A1
Host-Based Bit String Conversion
Reflow Endurance Improvements in Triple-Level Cell Nand Flash
Source Line Management for Memory Cells with Floating Gates
Three Dimensional Memory Devices
Apparatuses and Methods for a Load Current Control Circuit for a Source Follower Voltage Regulator
Storage Device Operation Orchestration
Modified Decode for Corner Turn
Drift Mitigation with Embedded Refresh
Ferroelectric Memory Cells Including Ferroelectric Crystalline Materials Having Polar and Chiral Crystal Structures, and Related Memory Devices
Application:
16/284,946 →
Publication:
US US20190189627A1
Memory Cells
Computer Modules with Small Thicknesses and Associated Methods of Manufacturing
Memory Sub-System for Decoding Non-Power-of-Two Addressable Unit Address Boundaries
Apparatuses and Methods for Memory Mat Refresh Sequencing
Apparatuses and Methods for Indirectly Detecting Phase Variations
Converting Floating-Point Operands into Universal Number Format Operands for Processing in a Multi-User Network
Acceleration Circuitry
Arithmetic and Logical Operations in a Multi-User Network
Power Translator Component
Reduced Footprint Fuse Circuit
Patent:
10,600,498 →
Application:
16/287,850 →
Memory Array And Methods Used In Forming A Memory Array
Double Threshold Controlled Scheduling of Memory Access Commands
Separate Read-Only Cache and Write-Read Cache in a Memory Sub-System
Use of Outstanding Command Queues for Separate Read-Only Cache and Write-Read Cache in a Memory Sub-System
Priority Scheduling in Queues to Access Cache Data in a Memory Sub-System
Eviction of a Cache Line Based on a Modification of a Sector of the Cache Line
Decision Feedback Equalizer
Memory Mapping Using Commands to Transfer Data and/or Perform Logic Operations
Dual Speed Memory
Command Bus in Memory
Background Operations in Memory
Techniques for Power Management Using Loopback
Power Management in Memory
Functional Signal Line Overdrive
Memory Having a Continuous Channel
Gate Noble Metal Nanoparticles
Ufs Based Idle Time Garbage Collection Management
Apparatuses and Methods for Transmitting an Operation Mode with a Clock
Patent:
10,630,294 →
Application:
16/292,074 →
Providing, in a Configuration Packet, Data Indicative of Data Flows in a Processor with a Data Flow Manager
Memory Cell Structures
Arbitration Techniques for Managed Memory
Arbitration Techniques for Managed Memory
Arbitration Techniques for Managed Memory
Management of Program Suspend and Resume Operations of a Memory Sub-System
Hybrid Logical to Physical Caching Scheme
Method and Apparatus for on-Chip Stress Detection
Methods and Apparatuses of a Two-Phase Flip-Flop with Symmetrical Rise and Fall Times
Methods of Compensating for Misalignment of Bonded Semiconductor Wafers
Methods of Forming Integrated Assemblies
Protected Regions Management of Memory
Dragging First Pass Read Level Thresholds Based on Changes in Second Pass Read Level Thresholds
Adjustment of Program Verify Targets Corresponding to a Last Programming Distribution and a Programming Distribution Adjacent to an Initial Programming Distribution
Dynamic Programing of Valley Margins of a Memory Cell
Adaptive Readahead Cache Manager Based on Detected Active Streams of Read Commands
Thermal Leveling
Dimension Control for Raised Lines
Two-Part Programming Methods
Channel Routing for Memory Devices
Methods of Forming Conductive Vias and Methods of Forming Memory Circuitry
Multi-Mode Voltage Pump and Control
Patterning Methods
Techniques for Secure Writes by Non-Privileged Users
Method to Vertically Align Multi-Level Cells
Uniformity Between Levels of a Multi-Level Signal
Integrated Circuity, DRAM Circuitry, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming DRAM Circuitry
Integrated Assemblies Comprising Memory Cells and Shielding Material Between the Memory Cells, and Methods of Forming Integrated Assemblies
NVMe DIRECT VIRTUALIZATION WITH CONFIGURABLE STORAGE
Refresh Circuitry
Proactive Corrective Actions in Memory Based on a Probabilistic Data Structure
Array of Cross Point Memory Cells and Methods of Forming an Array of Cross Point Memory Cells
Input Buffer Circuit Having Differential Amplifier
Memory Cells Having Electrically Conductive Nanodots and Apparatus Having Such Memory Cells
Apparatuses and Methods of Entering Unselected Memories into a Different Power Mode During Multi-Memory Operation
Apparatuses for Reducing Clock Path Power Consumption in Low Power Dynamic Random Access Memory
Apparatuses and Methods Including Anti-Fuses and for Reading and Programming of Same
Apparatuses and Methods for Providing Multiphase Clock Signals
Hybrid Memory Device Using Different Types of Capacitors and Operating Method Thereof
High Speed Signal Adjustment Circuit
Semiconductor Device Having Cam That Stores Address Signals
Memory Array Data Structure for Posit Operations
Sequential Memory Access Operations
Shifting Data in Sensing Circuitry
Cross-Point Memory and Methods for Forming of the Same
Methods of Operating a Memory with Redistribution of Received Data
Host Controlled Enablement of Automatic Background Operations in a Memory Device
Apparatus for Receiving or Transmitting Voltage Signals
Data Lines Updating for Data Generation
Apparatus and Methods Including a Bipolar Junction Transistor Coupled to a String of Memory Cells
Run-Time Code Execution Validation
Error Identification in Executed Code
Block Chain Based Validation of Memory Commands
Secure Device Communication
Secure Communication in Accessing a Network
Over-The-Air Update Validation
Application:
16/362,790 →
Publication:
US US20200310776A1
Using Memory as a Block in a Block Chain
Secure Communication Between a Vehicle and a Remote Device
Patent:
10,749,680 →
Application:
16/362,814 →
Secure Emergency Vehicular Communication
Secure Device Coupling
Secure Sensor Communication
Local Ledger Block Chain for Secure Updates
Secure Medical Apparatus Communication
Secure Vehicular Part Communication
Data Attestation in Memory
Verifying Vehicular Identity
Secure Communication for a Key Exchange
Secure Wireless Communication Between Implants and Apparatus
Validating an Electronic Control Unit of a Vehicle
Local Ledger Block Chain for Secure Electronic Control Unit Updates
Validating Data Stored in Memory Using Cryptographic Hashes
Secure Communication in a Traffic Control Network
Verification of Identity Using a Secret Key
Secure Monitoring Using Block Chain
Selector Threshold Compensation
Secure Communication Between an Intermediary Device and a Network
Memory Cells, Semiconductor Devices Comprising Memory Cells, and Related Systems
Secure Data Removal
Selective Dielectric Deposition
Centralized Placement of Command and Address in Memory Devices
Centralized Placement of Command and Address Swapping in Memory Devices
Routing for Power Signals Including a Redistribution Layer
Apparatuses and Methods Using Dummy Cells Programmed to Different States
Self-Reference for Ferroelectric Memory
Apparatuses and Methods for Photonic Communication and Photonic Addressing
Extended Memory Operations
Apparatuses and Methods for Parity Determination Using Sensing Circuitry
Phase Lock Circuitry Using Frequency Detection
Serializer
Patent:
10,573,373 →
Application:
16/368,728 →
Methods of Sealing Openings, and Methods of Forming Integrated Assemblies
Patent:
10,418,275 →
Application:
16/369,150 →
Semiconductor Recess Formation
Predictive Power Management
Current Monitoring in Semiconductor Packages
Phase Clock Correction
Semiconductor Devices Having Conductive Vias and Methods of Forming the Same
Apparatuses and Methods for Compensation of Sense Amplifiers
Enhancing Nucleation in Phase-Change Memory Cells
Clock Signal Generator Generating Four-Phase Clock Signals
Determining Overlay of Features of a Memory Array
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge Storage Transistor And Arrays Of Elevationally-Extending Strings Of Memory Cells Comprising A Programmable Charge Storage Transistor
Resetting Clock Divider Circuitry Prior to a Clock Restart
Memory Including Search Logic
Semiconductor Devices Including Redistribution Layers
Driver Circuit Equipped with Power Gating Circuit
Methods for Independent Memory Bank Maintenance and Memory Devices and Systems Employing the Same
Methods for Independent Memory Bank Maintenance and Memory Devices and Systems Employing the Same
Voltage Correction Computations for Memory Decision Feedback Equalizers
Apparatuses and Methods for Staggered Timing of Targeted Refresh Operations
Apparatuses and Methods for Targeted Refreshing of Memory
Apparatuses and Methods for Providing Additional Drive to Multilevel Signals Representing Data
Methods and Systems for Using State Vector Data in a State Machine Engine
Semiconductor Device Assembly with Heat Transfer Structure Formed from Semiconductor Material
Interconnect Structures with Intermetallic Palladium Joints and Associated Systems and Methods
Solid State Lighting Devices with Accessible Electrodes and Methods of Manufacturing
Ultrathin Solid State Dies and Methods of Manufacturing the Same
Architecture for 3-D Nand Memory
Virtual Address Table
System in Package (Sip) with Dual Laminate Interposers
Application:
16/378,260 →
Publication:
US US20190237436A1
Apparatuses and Methods for Controlling Driving Signals in Semiconductor Devices
Dual Sided Fan-Out Package Having Low Warpage Across All Temperatures
Semiconductor Structure Formation
Memory Array with Multiplexed Digit Lines
Apparatuses and Methods for Providing Internal Clock Signals of Different Clock Frequencies in a Memory Device
Output Buffer Circuit with Non-Target Odt Function
Patent:
10,529,412 →
Application:
16/379,635 →
Stack Access Control for Memory Device
Power Supply Wiring in a Semiconductor Memory Device
Reference Voltage Management
Patent:
10,692,557 →
Application:
16/381,702 →
Content Addressable Memory Systems with Content Addressable Memory Buffers
Writing and Querying Operations in Content Addressable Memory Systems with Content Addressable Memory Buffers
Apparatuses and Methods for Controlling Word Line Discharge
Methods Used in Forming a Memory Array Comprising Strings of Memory Cells
Semiconductor Processing Applying Supercritical Drying
Method and Optoelectronic Structure Providing Polysilicon Photonic Devices with Different Optical Properties in Different Regions
Parallel Access to Volatile Memory by A Processing Device for Machine Learning
Integrated Antenna Using Through Silicon Vias
Methods for Acquiring Planar View Stem Images of Device Structures
Patent:
10,401,265 →
Application:
16/135,821 →
Apparatuses and Methods for Providing Internal Memory Commands and Control Signals in Semiconductor Memories
Apparatuses and Methods for Determining a Phase Relationship Between an Input Clock Signal and a Multiphase Clock Signal
Wafer-Level Methods of Fabricating Semiconductor Device Packages and Related Packages
Methods of Forming Integrated Assemblies Having Conductive Material Along Sidewall Surfaces of Semiconductor Pillars
Automatic Collection of Autonomous Vehicle Logging Data
Devices Having a Transistor and a Capacitor Along a Common Horizontal Level, and Methods of Forming Devices
Methods of Forming Integrated Assemblies
Apparatuses and Methods for Input Receiver Circuits and Receiver Masks for Same
Security Managers and Methods for Implementing Security Protocols in a Reconfigurable Fabric
Real-Time Selection of Data to Collect in Autonomous Vehicle
Memory Mapping for Hibernation
Synchronous Memory Bus Access to Storage Media
Semiconductor Devices and Systems with Channel Openings or Pillars Extending Through a Tier Stack, and Methods of Formation
Nonvolatile Storage Using Low Latency and High Latency Memory
Integrated Assemblies Having Charge-Trapping Material Arranged in Vertically-Spaced Segments, and Methods of Forming Integrated Assemblies
Patent:
10,593,695 →
Application:
16/162,672 →
Memory Systems having Controllers Embedded in Packages of Integrated Circuit Memory
Semiconductor Device Packages with Enhanced Heat Management and Related Systems
Silicon Interposer with Fuse-Selectable Routing Array
Patent:
10,580,720 →
Application:
16/166,428 →
Accelerate Data Access in Memory Systems via Data Stream Segregation
Application:
16/166,624 →
Publication:
US US20190243771A1
CPU Cache Flushing to Persistent Memory
Apparatuses and Methods for Setting a Duty Cycle Adjuster for Improving Clock Duty Cycle
Apparatuses and Methods for Setting a Duty Cycle Adjuster for Improving Clock Duty Cycle
Apparatuses and Methods for Setting a Duty Cycle Adjuster for Improving Clock Duty Cycle
Functional Blocks Implemented by 3D Stacked Integrated Circuit
Power and Temperature Management for Functional Blocks Implemented by a 3D Stacked Integrated Circuit
3D Stacked Integrated Circuits Having Functional Blocks Configured to Accelerate Artificial Neural Network (ANN) Computation
Patent:
10,461,076 →
Application:
16/169,919 →
Universal Pointers for Data Exchange in a Computer System having Independent Processors
Integrated Assemblies Which Include Stacked Memory Decks, and Methods of Forming Integrated Assemblies
Kits for Enhanced Cooling of Components of Computing Devices and Related Computing Devices, Systems and Methods
Redistribution-Layer Fanout Package Stiffener
Method and Apparatus for Precharge and Refresh Control
System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network
Memory Arrays, and Methods of Forming Memory Arrays
Data Link Between Volatile Memory and Non-Volatile Memory
Graphics Processing Unit and High Bandwidth Memory Integration Using Integrated Interface and Silicon Interposer
Graphics Processing Unit and High Bandwidth Memory Integration Using Integrated Interface and Silicon Interposer
Tsv Redundancy and Tsv Test Select Scheme
Patent:
10,468,386 →
Application:
16/183,961 →
Virtual Ground Sensing Circuitry and Related Devices, Systems, and Methods for Crosspoint Ferroelectric Memory
Virtual Ground Sensing Circuitry and Related Devices, Systems, and Methods for Crosspoint Ferroelectric Memory
Integrated Assemblies Having Ferroelectric Transistors with Heterostructure Active Regions
Memory Systems and Memory Writing Methods
Sensor Fusion to Determine Reliability of Autonomous Vehicle Operation
Methods of Forming a Semiconductor Device, and Related Semiconductor Devices and Systems
Patent:
10,566,241 →
Application:
16/194,926 →
Electronic Devices Comprising a Source Below Memory Cells and Related Systems
Apparatuses and Methods for a Multi-Bit Duty Cycle Monitor
Apparatuses and Methods for Using Look-Ahead Duty Cycle Correction to Determine Duty Cycle Adjustment Values While a Semiconductor Device Remains in Operation
Antenna Formation by Integrated Metal Layer or Redistribution Layer
Apparatuses Including 3D Memory Arrays, Methods of Forming the Apparatuses, and Related Electronic Systems
Integrated Assemblies Having Body Contact Regions Proximate Transistor Body Regions; and Methods Utilizing Bowl Etches During Fabrication of Integrated Assemblies
Integrated Assemblies Comprising Vertically-Stacked Decks of Memory Arrays
Integrated Assemblies Comprising Redundant Wiring Routes, and Integrated Circuit Decks Having Openings Extending Therethrough
Patent:
10,607,923 →
Application:
16/213,362 →
Microelectronic Devices Including Capacitor Structures and Methods of Forming Microelectronic Devices
Neural Networks and Systems for Decoding Encoded Data
Methods of Forming a Semiconductor Device
Redistribution Layers with Carbon-Based Conductive Elements, Methods of Fabrication and Related Semiconductor Device Packages and Systems
Anisotropic Conductive Film with Carbon-Based Conductive Regions and Related Semiconductor Assemblies, Systems, and Methods
Systems Enabling Lower-Stress Processing of Semiconductor Device Structures and Related Structures
Integrated Assemblies Having Threshold-Voltage-Inducing-Structures Proximate Gated-Channel-Regions, and Methods of Forming Integrated Assemblies
Methods for Device Fabrication Using Pitch Reduction
Apparatuses Having Compensator Lines Along Wordlines and Independently Controlled Relative to the Wordlines
Methods of Incorporating Leaker-Devices into Capacitor Configurations to Reduce Cell Disturb, and Capacitor Configurations Incorporating Leaker-Devices
Apparatuses and Methods for Transferring Data from Memory on a Data Path
Sense Amplifier Signal Boost
Polishing System, Polishing Pad, and Related Methods
Memory Controller
Integrated Assemblies Having Capacitive Units, and Having Resistive Structures Coupled with the Capacitive Units
Apparatuses, Multi-Chip Modules and Capacitive Chips
Integrated Assemblies and Methods of Forming Integrated Assemblies
Mixing Coefficient Data Specific to a Processing Mode Selection Using Layers of Multiplication/Accumulation Units for Wireless Communication
Arrays of Memory Cells and Methods of Forming an Array of Vertically Stacked Tiers of Memory Cells
Integrated Structures
Methods of Forming Assemblies Including Semiconductor Material with Heavily-Doped and Lightly-Doped Regions
Integrated Assemblies Having Polycrystalline First Semiconductor Material Adjacent Conductively-Doped Second Semiconductor Material
Integrated Assemblies Comprising Hydrogen Diffused Within Two or More Different Semiconductor Materials, and Methods of Forming Integrated Assemblies
Semiconductor Device with Flexible Circuit for Enabling Non-destructive Attaching and Detaching of Device to System Board
Apparatuses and Methods for Generating Probabilistic Information with Current Integration Sensing
Apparatuses and Methods for Repairing Memory Devices Including a Plurality of Memory Die and an Interface
Deferred Error Code Correction with Improved Effective Data Bandwidth Performance
Two-Stage Flash Programming for Embedded Systems
Vector Processor with Vector First and Multiple Lane Configuration
Driver Assistance for Non-Autonomous Vehicle in an Autonomous Environment
Cryptographically Secure Mechanism for Remotely Controlling an Autonomous Vehicle
Secure Vehicle Communications Architecture for Improved Blind Spot and Driving Distance Detection
Electric Vehicle Charging Station System
Vehicle Accident Management Using Peer-to-Peer Networks and Systems
Verifying Identity of an Emergency Vehicle During Operation
Distributed Secure Array Using Intra-Dice Communications to Perform Data Attestation
Secure Communications Amongst Connected Dice
Generating an Identity for a Computing Device Using a Physical Unclonable Function
Verifying Identity of a Vehicle Entering a Trust Zone
Cryptography-Based Platooning Mechanism for Autonomous Vehicle Fleet Management
Remotely Managing Devices Using Blockchain and Dice-Riot
Methods of Filling Horizontally-Extending Openings of Integrated Assemblies
Semiconductor Memory Device Including Output Buffer
Memory Arrays
Capacitors, Integrated Assemblies Including Capacitors, and Methods of Forming Integrated Assemblies
Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Automotive Electronic Control Unit Pre-Booting for Improved Man Machine Interface Performance
Automotive Electronic Control Unit Reliability and Safety During Power Standby Mode
Integrated Assemblies Having Charge-Trapping Material Arranged in Vertically-Spaced Segments, and Methods of Forming Integrated Assemblies
Onboarding Software on Secure Devices to Generate Device Identities for Authentication with Remote Servers
Polishing Apparatuses and Polishing Methods
Fuses, and Methods of Forming and Using Fuses
Memory Devices and Related Methods
Integrated Assemblies Which Include Two Different Types of Silicon Nitride, and Methods of Forming Integrated Assemblies
Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors
Conductive Interconnects Suitable for Utilization in Integrated Assemblies, and Methods of Forming Conductive Interconnects
Assemblies Which Include Wordlines Having a First Metal-Containing Material at Least Partially Surrounding a Second Metal-Containing Material and Having Different Crystallinity than the Second Metal-Containing Material
Assemblies Which Include Ruthenium-Containing Conductive Gates
Thermal Control Component
Patent:
893,484 →
Application:
29/673,181 →
Memory Address Translation from Object Specific Virtual Address Spaces to a Physical Address Space
Application:
62/725,092 →
Stacked Memory Routing Techniques
Application:
62/734,018 →
Dynamically Configuring Transmission Lines of a Bus
Application:
62/741,845 →
Adapting Channel Current
Application:
62/744,907 →
Offset Cancellation
Application:
62/746,250 →
Memory Command Verification
Application:
62/746,274 →
Command Block Management
Application:
62/746,284 →
Flexible Bus Management
Application:
62/746,287 →
Error Correction Management for a Memory Device
Application:
62/746,295 →
Methods and Devices for Error Correction
Application:
62/746,316 →
Memory Arrays And Methods Used In Forming A Memory Array
Application:
62/746,728 →
Controlled Heating of a Memory Device
Application:
62/749,441 →
Mode-Dependent Heating of a Memory Device
Application:
62/749,454 →
Multi-Level Receiver with Termination-Off Mode
Application:
62/749,468 →
Temperature-Based Memory Management
Application:
62/767,780 →
Configuring Command/Address Channel for Memory
Application:
62/771,420 →
Multi-Level Signaling for a Memory Device
Application:
62/776,089 →
Dynamic Control of Error Management and Signaling
Application:
62/779,024 →
Reporting Control Information Errors
Application:
62/781,989 →
Systems and Techniques for Accessing Multiple Memory Cells Concurrently
Application:
62/782,015 →
Memory Device Low Power Mode
Application:
62/782,661 →
Multiplexed Signal Development in a Memory Device
Application:
62/783,388 →
Vertical 2-Transistor Memory Cell
Application:
62/785,119 →
Memory Device Having Shared Read/Write Access Line for 2-Transistor Vertical Memory Cell
Application:
62/785,136 →
Memory Device Having Shared Read/Write Data Line for 2-Transistor Vertical Memory Cell
Application:
62/785,142 →
Memory Device Having Shared Access Line for 2-Transistor Vertical Memory Cell
Application:
62/785,150 →
Memory Device Having 2-Transistor Vertical Memory Cell
Application:
62/785,154 →
Vertical 3D Single Word Line Gain Cell with Shared Read/Write Bit Line
Application:
62/785,159 →
Physical Unclonable Function at a Memory Device
Application:
62/786,753 →
Method and Apparatus for on-Chip Stress Detection
Application:
62/786,762 →
Arbitration Techniques for Managed Memory
Application:
62/786,764 →
Multi-Page Parity Protection with Power Loss Handling
Application:
62/786,889 →
Standby Biasing Techniques to Reduce Read Disturbs
Application:
62/786,930 →
Arbitration Techniques for Managed Memory
Application:
62/786,944 →
Arbitration Techniques for Managed Memory
Application:
62/786,949 →
Three-Dimensional Dynamic Random-Access Memory Array
Application:
62/786,985 →
Semiconductor Packages with Pass-Through Clock Traces and Associated Systems and Methods
Application:
62/787,012 →
Functional Signal Line Overdrive
Application:
62/787,018 →
Configurable Data Path for Memory Modules
Application:
62/787,039 →
Channel Modulation for a Memory Device
Application:
62/793,585 →
Refresh Rate Management for Memory
Application:
62/804,270 →
On-Die Memory Power Analytics and Management
Application:
62/804,329 →
Refresh Rate Control for a Memory Device
Application:
62/804,469 →
Memory Device with Configurable Error Correction Modes
Application:
62/807,520 →
Stacked Memory Device Interface and Method
Application:
62/809,281 →
Stacked Memory Dice for Combined Access Operations
Application:
62/810,037 →
Extended Error Detection for a Memory Device
Application:
62/812,515 →
Integrated Assemblies Having Shield Lines Between Digit Lines, and Methods of Forming Integrated Assemblies
Application:
62/814,664 →
Receive-Side Crosstalk Cancelation
Application:
62/816,480 →
Memory Device Interface and Method
Application:
62/816,731 →
Bit String Conversion
Application:
62/817,792 →
Bit String Conversion
Application:
62/817,863 →
Memory Device Interface and Method
Application:
62/826,422 →
Network Based Pico Framework with Flexible Remote Loading and Attached Computational Storage
Application:
62/826,591 →
Large Data Read Techniques
Application:
62/830,935 →
Semiconductor Devices Comprising Transistors Having Increased Threshold Voltage and Related Methods and Systems
Application:
62/743,059 →
Transistors Including Heterogeneous Channels, and Related Semiconductor Devices, Memory Devices, Electronic Systems, and Methods
Application:
62/743,075 →
Semiconductor Devices Including Vertical Transistors, and Related Methods
Application:
62/743,078 →
Semiconductor Devices and Electronic Systems Including Vertical Transistors, and Related Methods
Application:
62/743,089 →
Methods of Forming a Semiconductor Device, and Related Semiconductor Devices, Memory Devices, and Electronic Systems
Application:
62/743,108 →
Methods of Forming a Semiconductor Device, and Related Semiconductor Devices, Memory Devices, and Electronic Systems
Application:
62/743,114 →
Semiconductor Devices Including Vertical Transistors Having Hydrogen Barrier Materials, and Related Methods
Application:
62/743,133 →
Semiconductor Devices Including Vertical Transistors, and Related Methods
Application:
62/743,139 →
Integrated Assemblies Having Semiconductor Oxide Channel Material, and Methods of Forming Integrated Assemblies
Application:
62/770,081 →
Integrated Assemblies Having Transistor Body Regions Coupled to Carrier-Sink-Structures; and Methods of Forming Integrated Assemblies
Application:
62/814,689 →
Interposer, Microelectronic Device Assembly Including Same and Methods of Fabrication
Application:
62/820,548 →
Method for Evaluating Efficacy of Prevention Maintenance for a Tool
Semiconductor Die Assemblies with Heat Sink and Associated Systems and Methods
Apparatuses and Methods Including Memory Access in Cross Point Memory
Packaged Microelectronic Devices and Methods for Manufacturing Packaged Microelectronic Devices
Volatile Memory Device Including Stacked Memory Cells
PCT:
PCT/US2018/047956 ↗
Command Selection Policy
PCT:
PCT/US2018/052921 ↗
3DI Solder Cup
PCT:
PCT/US2018/053951 ↗
Apparatuses and Methods for Providing Bias Signals in a Semiconductor Device
PCT:
PCT/US2018/063144 ↗
Apparatuses and Methods for Data Transmission Offset Values in Burst Transmissions
PCT:
PCT/US2018/063673 ↗
Apparatuses and Methods for Duty Cycle Error Correction of Clock Signals
PCT:
PCT/US2018/065738 ↗
Techniques to Update a Trim Parameter in Non-Volatile Memory
PCT:
PCT/US2018/065769 ↗
Apparatuses and Methods for Providing Frequency Divided?Clocks
PCT:
PCT/US2018/066408 ↗
Auto-Referenced Memory Cell Read Techniques
PCT:
PCT/US2018/066653 ↗
Auto-Referenced Memory Cell Read Techniques
PCT:
PCT/US2018/067287 ↗
Multi-Bias Level Generation and Interpolation
PCT:
PCT/US2018/050517 ↗
Analog Multiplexing Scheme for Decision Feedback Equalizers
PCT:
PCT/US2018/050518 ↗
Memory Decision Feedback Equalizer Bias Level Generation
PCT:
PCT/US2018/050738 ↗
Techniques for Command Synchronization in a Memory Device
PCT:
PCT/US2018/051508 ↗
Systems and Methods for Generating Stagger Delays in Memory Devices
PCT:
PCT/US2018/051709 ↗
Methods and Apparatuses of a Two-Phase Flip-Flop with Symmetrical Rise and Fall Times
PCT:
PCT/US2018/052445 ↗
Apparatuses and Methods Including Memory Commands for Semiconductor Memories ?
PCT:
PCT/US2018/053578 ↗
Apparatuses and Methods for Providing Multiphase Clock Signals
PCT:
PCT/US2018/053810 ↗
Devices Having a Transistor and a Capacitor Along a Common Horizontal Level, and Methods of Forming Devices
PCT:
PCT/US2018/054296 ↗
Apparatuses and Methods for Parallel I/O Operations in a Memory
PCT:
PCT/US2018/054673 ↗
Methods of Forming a Transistor and Methods of Forming an Array of Memory Cells
PCT:
PCT/US2018/055407 ↗
A Construction of Integrated Circuitry and Dram Construction
PCT:
PCT/US2018/055410 ↗
Autocorrelation and Memory Allocation for Wireless Communication
PCT:
PCT/US2018/055662 ↗
Apparatus and Methods for Refreshing Memory
PCT:
PCT/US2018/055821 ↗
Systems and Methods for Improving Input Signal Quality in Memory Devices
PCT:
PCT/US2018/055844 ↗
Systems and Methods for Conserving Power in Signal Quality Operations for Memory Devices
PCT:
PCT/US2018/055847 ↗
Internal Write Adjust for a Memory Device
PCT:
PCT/US2018/055852 ↗
Data Strobe Gating
PCT:
PCT/US2018/055857 ↗
Memory Device Parallelizer
PCT:
PCT/US2018/055866 ↗
Dqs Gating in a Parallelizer of a Memory Device
PCT:
PCT/US2018/056332 ↗
Apparatuses and Methods for Setting a Duty Cycle Adjuster for Improving Clock Duty Cycle
PCT:
PCT/US2018/056785 ↗
Apparatus and Methods for Refreshing Memory ?
PCT:
PCT/US2018/056871 ↗
Wireless Devices and Systems Including Examples of Configuration During an Active Time Period
PCT:
PCT/US2018/057859 ↗
Namespace Mapping Structural Adjustment in Non-Volatile Memory Devices
PCT:
PCT/US2018/059377 ↗
Input Buffer Circuit
PCT:
PCT/US2018/063138 ↗
Self-Learning in Distributed Architecture for Enhancing Artificial Neural Network
PCT:
PCT/US2018/063669 ↗
Stress Tuned Stiffeners for Micro Electronics Package Warpage Control
PCT:
PCT/US2018/051544 ↗
Read Retry Scratch Space
PCT:
PCT/US2019/013026 ↗
Methods and Apparatuses for Dynamic Step Size for Impedance Calibration of a Semiconductor Device
PCT:
PCT/US2019/013522 ↗
Determination of a Match Between Data Values Stored by Several Arrays
PCT:
PCT/US2019/013613 ↗
Logical Operations Using Memory Cells
PCT:
PCT/US2019/013765 ↗
Determination of a Match Between Data Values Stored by Three or More Arrays
PCT:
PCT/US2019/014138 ↗
Artificial Neural Network Integrity Verification
PCT:
PCT/US2019/015067 ↗
Self-Referencing Sensing Schemes with Coupling Capacitance
PCT:
PCT/US2019/015083 ↗
A Storage Backed Memory Package Save Trigger
PCT:
PCT/US2019/015625 ↗
Tapered Memory Cell Profiles
PCT:
PCT/US2019/015671 ↗
Dopant-Modulated Etching for Memory Devices
PCT:
PCT/US2019/015678 ↗
Memory Cells with Asymmetrical Electrode Interfaces
PCT:
PCT/US2019/015683 ↗
Firmware Update in a Storage Backed Memory Package
PCT:
PCT/US2019/015917 ↗
Status Management in Storage Backed Memory Package
PCT:
PCT/US2019/016009 ↗
Key Encryption Handling
PCT:
PCT/US2019/016117 ↗
Doped Titanium Nitride Materials for Dram Capacitors, and Related Semiconductor Devices, Systems, and Methods
PCT:
PCT/US2019/016254 ↗
Apparatuses and Methods for Duty Cycle Distortion Correction of Clocks
PCT:
PCT/US2019/016528 ↗
Partial Save of Memory
PCT:
PCT/US2019/016623 ↗
Generating and Using Invertible, Shortened Bose-Chaudhuri-Hocquenghem Codewords
PCT:
PCT/US2019/016678 ↗
Backup Operations from Volatile to Non-Volatile Memory
PCT:
PCT/US2019/016831 ↗
Backup Operations from Volatile to Non-Volatile Memory
PCT:
PCT/US2019/016843 ↗
Backup Operations from Volatile to Non-Volatile Memory
PCT:
PCT/US2019/016854 ↗
Interface for Memory Having a Cache and Multiple Independent Arrays
PCT:
PCT/US2019/019066 ↗
Three Dimensional Memory Devices
PCT:
PCT/US2019/019144 ↗
Apparatuses and Methods for Adjusting a Phase Mixer Circuit
PCT:
PCT/US2019/019793 ↗
Differential Amplifier Schemes for Sensing Memory Cells
PCT:
PCT/US2019/020003 ↗
Methods and Apparatuses for Aligning Read Data in a Stacked Semiconductor Device
PCT:
PCT/US2019/020783 ↗
Tracking Data Temperatures of Logical Block Addresses
PCT:
PCT/US2019/021169 ↗
Sub-Threshold Voltage Leakage Current Tracking
PCT:
PCT/US2019/021581 ↗
Hybrid Memory System
PCT:
PCT/US2019/021960 ↗
Channel Routing for Memory Devices
PCT:
PCT/US2019/022307 ↗
Health Characteristics of a Memory Device
PCT:
PCT/US2019/022403 ↗
Clustered Parity for Nand Data Placement Schema
PCT:
PCT/US2019/022576 ↗
Nand Data Placement Schema
PCT:
PCT/US2019/022587 ↗
Hybrid Memory System
PCT:
PCT/US2019/022665 ↗
Hybrid Memory System
PCT:
PCT/US2019/023054 ↗
Apparatuses and Methods for Sensing Memory Cells
PCT:
PCT/US2019/023502 ↗
Storage Device Authenticated Modification
PCT:
PCT/US2019/023551 ↗
Apparatuses and Methods for Counter Update Operations
PCT:
PCT/US2019/024201 ↗
Determining Whether a Vehicle Should Be Configured for a Different Region
PCT:
PCT/US2019/024206 ↗
Logical-To-Physical Data Structures
PCT:
PCT/US2019/024244 ↗
Sensing Operations in Memory
PCT:
PCT/US2019/024728 ↗
Memory Management
PCT:
PCT/US2019/025134 ↗
Transmission of Vehicle Route Information by Passive Devices
PCT:
PCT/US2019/025149 ↗
Error Correction Using Hierarchical Decoders
PCT:
PCT/US2019/025161 ↗
Transaction Metadata
PCT:
PCT/US2019/025169 ↗
An Image Processor Formed in an Array of Memory Cells
PCT:
PCT/US2019/026453 ↗
Command Selection Policy with Read Priority
PCT:
PCT/US2019/026974 ↗
Memory Systems Having Controllers Embedded in Packages of Integrated Circuit Memory
PCT:
PCT/US2019/013841 ↗
Memory Module Data Object Processing Systems and Methods
PCT:
PCT/US2019/014036 ↗
Enhanced Error Correcting Code Capability Using Variable Logical to Physical Associations of a Data Block
PCT:
PCT/US2019/014045 ↗
Storing Critical Data at a Memory System
PCT:
PCT/US2019/014051 ↗
Identifying a Read Operation for a Storage Device Based on a Workload of a Host System
PCT:
PCT/US2019/014181 ↗
Accelerate Data Access in Memory Systems via Data Stream Segregation
PCT:
PCT/US2019/014205 ↗
Memory Access Communications Through Message Passing Interface Implemented in Memory Systems
PCT:
PCT/US2019/014216 ↗
Memory Virtualization for Accessing Heterogeneous Memory Components
PCT:
PCT/US2019/014275 ↗
Remote Direct Memory Access in Multi-Tier Memory Systems
PCT:
PCT/US2019/014285 ↗
Data Storage Device Idle Time Processing
PCT:
PCT/US2019/014765 ↗
End of Service Life of Data Storage Devices
PCT:
PCT/US2019/014774 ↗
Synchronous Memory Bus Access to Storage Media
PCT:
PCT/US2019/014827 ↗
Self Interference Noise Cancellation to Support Multiple Frequency Bands
PCT:
PCT/US2019/014897 ↗
Multiple Memory Type Memory Module Systems and Methods
PCT:
PCT/US2019/014982 ↗
Cpu Cache Flushing to Persistent Memory
PCT:
PCT/US2019/015361 ↗
Memory Controller
PCT:
PCT/US2019/015463 ↗
Memory Controller with Programmable Atomic Operations
PCT:
PCT/US2019/015467 ↗
Optimization of Data Access and Communication in Memory Systems
PCT:
PCT/US2019/015602 ↗
Mitigating a Voltage Condition of a Memory Cell in a Memory Sub-System
PCT:
PCT/US2019/016421 ↗
Integrated Assemblies Having Dielectric Regions Along Conductive Structive Structures, and Methods of Forming Integrated Assemblies
PCT:
PCT/US2019/016689 ↗
Methods of Sealing Openings, and Methods of Forming Integrated Assemblies
PCT:
PCT/US2019/016695 ↗
Integrated Circuitry, Dram Circuitry, and Methods Used in Forming Integrated Circuitry
PCT:
PCT/US2019/016824 ↗
Half-Width, Double Pumped Data Path
PCT:
PCT/US2019/016974 ↗
Performing an Operation on a Memory Cell of a Memory System at a Frequency Based on Temperature
PCT:
PCT/US2019/017104 ↗
Providing Recovered Data to a New Memory Cell at a Memory Sub-System Based on an Unsuccessful Error Correction Operation
PCT:
PCT/US2019/017333 ↗
Systems and Methods for a Centralized Command Address Input Buffer
PCT:
PCT/US2019/017707 ↗
Performing an Additional Decoding Operation on an Identified Set of Bits of a Data Block
PCT:
PCT/US2019/018820 ↗
Performing a Decoding Operation to Simulate Switching a Bit of an Identified Set of Bits of a Data Block
PCT:
PCT/US2019/018823 ↗
Resource Sharing Among Vehicle Applications Connected via a Bus
PCT:
PCT/US2019/018946 ↗
Self-Selecting Memory Array with Horizontal Access Lines
PCT:
PCT/US2019/019126 ↗
Generating Parity Data Based on a Characteristic of a Stream of Data
PCT:
PCT/US2019/019232 ↗
Black Box Data Recorder for Autonomous Driving Vehicle
PCT:
PCT/US2019/019562 ↗
Black Box Data Recorder with Artificial Intelligence Processor in Autonomous Driving Vehicle
PCT:
PCT/US2019/019651 ↗
Arrays of Memory Cells Individually Comprising a Capacitor and a Transistor and Methods of Forming Such Arrays
PCT:
PCT/US2019/020206 ↗
Techniques for Power Management Using Loopback
PCT:
PCT/US2019/020529 ↗
Methods for Detecting and Mitigating Memory Media Degradation and Memory Devices Employing the Same
PCT:
PCT/US2019/020598 ↗
Internal Write Leveling Circuitry
PCT:
PCT/US2019/020785 ↗
Optimization of Memory Systems Based on Performance Goals
PCT:
PCT/US2019/021683 ↗
Power Management, Dynamic Routing and Memory Management for Autonomous Driving Vehicles
PCT:
PCT/US2019/023168 ↗
Specifying Media Type in Write Commands
PCT:
PCT/US2019/024265 ↗
Determining Autonomous Vehicle Status Based on Mapping of Crowdsourced Object Data
PCT:
PCT/US2019/025112 ↗
Multi-Stage Memory Sensing
PCT:
PCT/US2019/025233 ↗
Memory Start Voltage Management
PCT:
PCT/US2019/025255 ↗
Integrated Assemblies Which Include Non-Conductive-Semiconductor-Material and Conductive-Semiconductor-Material, and Methods of Forming Integrated Assemblies
PCT:
PCT/US2019/025490 ↗
Integrated Circuit, Construction of Integrated Circuitry, and Method of Forming an Array
PCT:
PCT/US2019/025509 ↗
Integrated Assemblies Having Metal-Containing Regions Coupled with Semiconductor Regions
PCT:
PCT/US2019/025594 ↗
Access Line Management for an Array of Memory Cells
PCT:
PCT/US2019/025636 ↗
Integrated Circuitry Construction, a Dram Construction, and a Method Used in Forming an Integrated Circuitry Construction
PCT:
PCT/US2019/025648 ↗
Integrated Circuitry Constructions
PCT:
PCT/US2019/025759 ↗
An Array of Recessed Access Devices and an Array of Memory Cells Individualy Comprising a Capacitor and a Transistor
PCT:
PCT/US2019/025935 ↗
Related Assignments
(18)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 10, 2018
From: VANKAYALA, VIJAYAKRISHNA J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047044/0045 →
Assignment of Assignor's Interest
Sep 17, 2018
From: SHIDO, TAIHEI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046893/0275 →
Assignment of Assignor's Interest
Sep 17, 2018
From: MA, YANTAO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046893/0162 →
Assignment of Assignor's Interest
Sep 18, 2018
From: CADLONI, GERALD L.; LIIKANEN, BRUCE A.; CHEW, FRANCIS; KOUDELE, LARRY J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046904/0703 →
Assignment of Assignor's Interest
Sep 18, 2018
From: EL-MANSOURI, ADAM S.; PORTER, JOHN D.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046903/0904 →
Assignment of Assignor's Interest
Sep 18, 2018
From: SCHUBERT, MARTIN F.; ODNOBLYUDOV, VLADIMIR
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046904/0339 →
Assignment of Assignor's Interest
Sep 18, 2018
From: BHATTACHARYYA, ARUP
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046903/0259 →
Assignment of Assignor's Interest
Sep 18, 2018
From: WALLACH, STEVEN JEFFREY
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046901/0112 →
Assignment of Assignor's Interest
Sep 19, 2018
From: TAKAHASHI, TSUGIO; LIANG, ZER
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046916/0857 →
Assignment of Assignor's Interest
Sep 19, 2018
From: SATOH, YASUO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046916/0745 →
Assignment of Assignor's Interest
Sep 20, 2018
From: ZHANG, YU; WU, JUNE; HE, YUAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046921/0016 →
Corrective Assignment to Correct the Spelling of the 2ND Inventor's Name Previously Recorded on Reel 046921 Frame 0016. Assignor(S) Hereby Confirms the Assignment.
Sep 25, 2018
From: ZHANG, YU; WU, JUN; HE, YUAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047153/0789 →
Assignment of Assignor's Interest
Oct 31, 2018
From: ROWLEY, MATTHEW D.; CARTER, DUSTIN J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047373/0972 →
Assignment of Assignor's Interest
Jan 24, 2019
From: MALSHE, ASHUTOSH; SINGIDI, HARISH REDDY; MUCHHERLA, KISHORE KUMAR; MILLER, MICHAEL G
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048125/0879 →
Supplement No. 3 to Patent Security Agreement
Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
Assignment of Assignor's Interest
May 9, 2019
From: KOYA, YOSHIHITO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 049133/0166 →
Release of Security Interest
Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
Release of Security Interest
Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →