Architecture for 3-D NAND memory
Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.
1. An apparatus, comprising:
multiple stacked memory arrays, including a first array of memory cell strings and a second array of memory cell strings stacked over the first array, each memory cell string extending vertically, and including multiple memory cells; and
a data plate associated with the first array and the second array, the data plate extending in a horizontal plane and being located between the first array and the second array, and the data plate being shared by memory cell strings in multiple rows and in multiple columns of the first array and in multiple rows and in multiple columns of the second array,
wherein the first and second memory arrays are configured in multiple blocks, and wherein the multiple blocks each includes a memory cell string from the first array and a memory cell string from the second array.
2. The apparatus of claim 1 , wherein the memory cell strings include NAND memory cell strings.
3. The apparatus of claim 1 , wherein each of the memory cell strings includes a memory cell region, with a drain select gate disposed between the memory cell region and a data plate to which the memory cell string is coupled.
4. The apparatus of claim 3 , wherein the drain select gate comprises multiple hierarchical select gates coupled between the memory cell region of the memory cell string and the data plate to which the memory cell string is coupled.
5. The apparatus of claim 1 , wherein each of the memory cell strings includes a source select gate disposed between a memory cell region and a source to which the memory cell string is coupled.
6. The apparatus of claim 1 , further comprising:
for each of the memory cell strings associated with the data plate, multiple select gates coupled between a memory cell region of the memory cell string and the data plate.
7. The apparatus of claim 1 , wherein the multiple select gates includes a first select gate configured to select at least one block of the multiple blocks.
8. An apparatus, comprising:
multiple stacked memory arrays, including a first array of vertical memory cell strings and a second array of vertical memory cell strings over the first array; and
a data plate associated with the first array and the second array, the data plate extending in a horizontal plane and being located between the first array and the second array, and the data plate being shared by memory cell strings in multiple rows and in multiple columns of the first array and in multiple rows and in multiple columns of the second array.
9. The apparatus of claim 8 , wherein a block in a respective row of blocks includes a memory cell string from the first array and a memory cell string from the second array.
10. The apparatus of claim 8 , wherein the memory cell strings include NAND memory cell strings.
11. The apparatus of claim 8 , wherein each memory cell string includes a memory cell region and a drain select gate between the memory cell region of the string and the data plate to which the string is coupled.
12. The apparatus of claim 8 , wherein each memory cell string includes a memory cell region and a source select gate between the memory cell region of the string and a source to which the string is coupled.
13. The apparatus of claim 8 , wherein the memory strings of the second array coupled to the shared data plate are substantially vertically aligned with memory strings of the first array coupled to the shared data plate.
14. A method, comprising:
selecting a first vertical memory cell string in a first array including multiple vertical memory cell strings, the first array stacked over a second array including multiple vertical memory cell strings, the first array being disposed over the second array, wherein a shared data plate extends in a horizontal plane and is located between the first array and the second array, wherein the shared data plate is shared by memory cell strings in multiple rows and in multiple columns of the first array and by memory cell strings in multiple rows and in multiple columns of the second array;
detecting a first data state of a memory cell within the first vertical memory cell string at a shared data detector;
selecting a second vertical memory cell string in the second array; and
detecting a second data state of a vertical memory cell within the second vertical memory cell string at the shared data detector,
wherein a block in a respective row of blocks includes the first vertical memory cell string from the first array and the second vertical memory cell string from the second array.
15. The method of claim 14 , wherein memory cell strings of the first array are coupled between a first source and a shared data plate.
16. The method of claim 14 , wherein memory cell strings in multiple rows and columns of the second array are coupled between a second source and the shared data plate.
17. The method of claim 14 , wherein the memory cell strings include NAND memory cell strings.
18. The method of claim 14 , wherein detecting the first data state includes detecting the first data state through the shared data plate.
19. The method of claim 14 , wherein detecting the second data state includes detecting the second data state through the shared data plate.
20. The method of claim 14 , wherein the memory strings of the second array coupled to the shared data plate are substantially vertically aligned with memory strings of the first array coupled to the shared data plate.