IP Library Granted Patent US 11,024,617
Granted Patent B2
US 11,024,617 · App. 16/172,624 · Granted Jun 1, 2021

Semiconductor packages having photon integrated circuit (PIC) chips

Inventor: Omar J. Bchir (San Marcos, CA)
Assignee: Micron Technology, Inc.
H01L25/167G02B6/12004G02B6/1225G02B6/421G02B6/4274G02B6/43H01L23/52H01L24/09H01L24/49
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Quick Facts
Patent No.
US 11,024,617
App. No.
16/172,624
Granted
Jun 1, 2021
Kind
B2
Abstract

Memory devices having optical I/O interfaces are described herein. In one embodiment, a memory device includes a plurality of memories coupled to a substrate, each memory including one or more photon integrated (PIC) chips for converting electrical signals to/from optical signals. The memory device can further include a plurality of optical fibers, wherein individual ones of the memories are optically coupled to at least one of the optical fibers. The memories can receive/transmit the optical signals over the optical fibers and can be electrically coupled to a power supply/ground via the substrate.

Claims (14)

1. A semiconductor package, comprising:

a substrate having an upper surface;

a semiconductor die having an upper surface and a lower surface, wherein the semiconductor die is coupled to the upper surface of the substrate via a first die-attach material extending between the lower surface of the semiconductor die and the upper surface of the substrate, wherein the semiconductor die includes bond pads at the upper surface of the semiconductor die, and wherein the semiconductor die includes analog driver circuitry;

a first photon integrated circuit (PIC) chip having an upper surface and a lower surface, wherein the first PIC chip is coupled to the upper surface of the substrate via a second die-attach material extending between the lower surface of the first PIC chip and the upper surface of the substrate, wherein the first PIC chip includes bond pads at the upper surface of the first PIC chip, and wherein the first PIC chip is electrically coupled to the semiconductor die via first wirebonds extending between the bond pads of the first PIC chip and corresponding ones of the bond pads of the semiconductor die;

a first optical fiber optically coupled to the first PIC chip, wherein the first PIC chip is configured to:

receive first optical signals over the first optical fiber;

convert the first optical signals into electrical signals; and

transmit the electrical signals over the first wirebonds to the semiconductor die;

a second PIC chip having an upper surface and a lower surface, wherein the second PIC chip is coupled to the upper surface of the substrate via a third die-attach material extending between the lower surface of the second PIC chip and the upper surface of the substrate, wherein the second PIC chip includes bond pads at the upper surface of the second PIC chip and a light source, and wherein the second PIC chip is electrically coupled to the semiconductor die via second wirebonds extending between the bond pads of the second PIC chip and corresponding ones of the bond pads of the semiconductor die; and

a second optical fiber optically coupled to the second PIC chip;

wherein the analog driver circuitry is configured to drive the light source to modulate second optical signals generated by the light source for transmission on the second optical fiber.

2. The semiconductor package of claim 1 wherein the second PIC chip includes a multiplexer configured to multiplex the modulated second optical signals for transmission on the second optical fiber.

3. The semiconductor package of claim 1 wherein the light source is integrally formed with the second PIC chip.

4. The semiconductor package of claim 1 wherein the first optical signals are multiplexed optical signals, and wherein the first PIC chip includes a demultiplexer configured to demultiplex the multiplexed optical signals.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2018
From: BCHIR, OMAR J.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047331/0505 →
Continuity (1)
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