IP Library Granted Patent US 10,871,923
Granted Patent B2
US 10,871,923 · App. 16/294,416 · Granted Dec 22, 2020

Management of program suspend and resume operations of a memory sub-system

Inventors: Jiangang Wu (Milpitas, CA); Sampath K. Ratnam (Boise, ID); Yang Zhang (Shanghai, CN); Guang Chang Ye (Shanghai, CN); Kishore Kumar Muchherla (Fremont, CA); Hong Lu (San Jose, CA); Karl D. Schuh (Santa Cruz, CA); Vamsi Pavan Rayaprolu (San Jose, CA)
Assignee: Micron Technology, Inc.
G06F3/0659G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 10,871,923
App. No.
16/294,416
Granted
Dec 22, 2020
Kind
B2
Abstract

A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.

Claims (52)

1. A method comprising:

executing, by a processing device, a program operation on a memory sub-system;

during execution of the program operation, receiving a request to execute a read operation on the memory sub-system;

in response to receiving the request to execute the read operation, executing a program suspend operation to suspend the program operation;

executing the read operation on the memory sub-system in response to a completion of the program suspend operation;

in response to a completion of the read operation, executing a program resume operation to resume the suspended program operation; and

establishing a program suspend delay period following execution of the program resume operation during which a subsequent read operation is stored in a queue to be executed following the program suspend delay period.

2. The method of claim 1 , further comprising:

in response to an expiration of the program suspend delay period, executing the subsequent read operation.

3. The method of claim 1 , wherein the read operation is associated with a multi-level cell (MLC) of the memory sub-system.

4. The method of claim 1 , further comprising recording a time of the executing of the program resume operation.

5. The method of claim 4 , wherein the program suspend delay period starts from the time of the executing of the program resume operation.

6. The method of claim 1 , further comprising:

maintaining a count corresponding to active read operations stored in the queue, wherein the executing of the program resume operation is further in response to determining that the count satisfies a threshold count value.

7. A system comprising:

a memory component; and

a processing device, operatively coupled with the memory component, to:

determine a program suspend delay period following execution of a program resume operation in response to receiving a first read operation associated with a memory sub-system;

during the program suspend delay period, receive a second read operation;

store the second read operation in a queue, the second read operation to be executed following the program suspend delay period; and

following an expiration of the program delay period, execute the second read operation that has been stored in the queue.

8. The system of claim 7 , wherein the processing device is further to:

maintain a count of active read operations in the queue;

determine that the count satisfies a threshold count value; and

issue a command corresponding to the program resume operation in response to determining that the count satisfies the threshold count value.

9. The system of claim 7 , wherein the processing device is further to:

execute a program operation on the memory sub-system; and

in response to receiving the first read operation, execute a program suspend operation to suspend the program operation.

10. The system of claim 9 , wherein the processing device is further to execute the first read operation following execution of the program suspend operation.

11. The system of claim 7 , wherein the processing device is further to:

maintain a first count corresponding to active read operations associated with the memory sub-system;

maintain a second count corresponding to active sequential read operations associated with the memory sub-system; and

in response to determining the first count satisfies a threshold count value and the second count satisfies the threshold count value, executing the program resume operation.

12. The system of claim 7 , wherein the processing device is further to execute a program suspend operation following expiration of the program suspend delay period.

13. The system of claim 12 , wherein the processing device is further to identify the first read operation is associated with a multi-level cell (MLC) of the memory sub-system.

14. The system of claim 7 , wherein the processing device is further to record a time of a start of the program resume operation, wherein the program suspend delay period starts from the time of the start of the program resume operation.

15. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

executing, by the processing device, a program operation on a memory sub-system;

during execution of the program operation, receiving a request to execute a read operation on the memory sub-system;

in response to receiving the request to execute the read operation, executing a program suspend operation to suspend the program operation;

executing the read operation on the memory sub-system in response to a completion of the program suspend operation;

in response to a completion of the read operation, executing a program resume operation to resume the suspended program operation; and

establishing a program suspend delay period following execution of the program resume operation during which a subsequent read operation is stored in a queue to be executed following the program suspend delay period.

16. The non-transitory computer readable medium of claim 15 , the operations further comprising:

in response to an expiration of the program suspend delay period, executing the subsequent read operation.

17. The non-transitory computer readable medium of claim 15 , wherein the read operation is associated with a multi-level cell (MLC) of the memory sub-system.

18. The non-transitory computer readable medium of claim 15 , the operations further comprising:

recording a time of the executing of the program resume operation.

19. The non-transitory computer readable medium of claim 18 , wherein the program suspend delay period starts from the time of the executing of the program resume operation.

20. The non-transitory computer readable medium of claim 15 , the operations further comprising:

maintaining a count corresponding to active read operations stored in the queue; and

in response to determining the count satisfies a threshold count value, executing the program resume operation.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2019
From: WU, JIANGANG; RATNAM, SAMPATH K.; ZHANG, YANG; YE, GUANG CHANG; MUCHHERLA, KISHORE KUMAR; RAYAPROLU, VAMSI PAVAN; LU, HONG; SCHUH, KARL D.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051090/0833 →
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →