Selectively controlling clock transmission to a data (DQ) system
View Patent ↗An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.
1. An apparatus, comprising:
input circuitry configured to receive a command and a global clocking signal, wherein the input circuitry generates a processed command based at least in part on the command;
a data (DQ) system configured to retrieve data from memory in response to the processed command; and
a read data enable delay (RQED) circuit communicatively coupled between the input circuitry and the DQ system, the RQED circuit comprising:
a first group of flip-flops configured to delay the processed command by a first duration;
a second group of flip-flops configured to selectively disable a delay locked loop clock signal based on the global clocking signal, wherein the global clocking signal is configured to transmit to the DQ system a second duration after the DQ system receives a processed command in response to the processed command comprising a read command; and
calculation circuitry configured to determine the first duration.
2. The apparatus of claim 1 , wherein the calculation circuitry is configured to determine the first duration based at least in part on a latency signal and a delay indication signal.
3. The apparatus of claim 1 , wherein the RQED circuit comprises shifter circuitry and an OR gate configured to selectively enable the delay locked loop clock signal a third duration before the DQ system is configured to receive the processed command in response to the processed command comprising the read command.
4. The apparatus of claim 3 , wherein the third duration is approximately equal to two clock transitions and the second duration is approximately equal to four clock transitions.
5. The apparatus of claim 1 , wherein the first group of flip-flops comprises four flip-flops, and wherein the second group of flip-flops comprises four flip-flops.
6. The apparatus of claim 1 , comprising:
a delay line configured to receive a command signal and to provide a delayed command signal, wherein the delay line is coupled between the input circuitry and the RQED circuit; and
wherein the RQED circuit comprises:
an edge starter configured to provide a clock enable signal responsive, at least in part, to a change in level of the command signal;
a gate circuit configured to provide a shift clock signal responsive, at least in part, to the clock enable signal; and
a shifter configured to capture and delay the command signal the first duration responsive, at least in part, to the shift clock signal, wherein the shifter comprises the first group of flip-flops and is coupled to a first flip-flop of the second group of flip-flops.
7. The apparatus of claim 1 , wherein the input circuitry comprises a delay line configured to receive the processed command and to provide a delayed command signal as the processed command to the RQED circuit, and wherein the RQED circuit comprises:
an edge starter configured to provide a clock enable signal responsive, at least in part, to a change in level of the processed command signal;
a first gate circuit configured to provide a shift clock signal responsive, at least in part, to the clock enable signal; and
a shifter comprising the first group of flip-flops, wherein the shifter is configured to capture and shift the delayed command signal by the first duration responsive, at least in part, to the shift clock signal, and wherein the shifter receives a calculation result from the calculation circuitry that determines the first duration; and
a second gate circuit coupled between the second group of flip-flops and the DQ system, wherein the second gate circuit is configured to:
receive the delay locked loop clock signal;
receive an enable signal generated at least in part by the second group of flip-flops; and
disable the delay locked loop clocking signal a second duration after the processed command is provided to the DQ system based on a logical result of the enable signal with the global clocking signal, wherein the second duration is determined at least in part by the second group of flip-flops, and wherein the second group of flip-flops are coupled in series.