Hybrid memory device using different types of capacitors and operating method thereof
A hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.
1. A method of operating a memory device, comprising:
receiving, from a controller, a first signal comprising a first read request for a first memory cell that comprises a ferroelectric capacitor and a first selection component;
transferring data from the first memory cell to a second memory cell that comprises a paraelectric capacitor and a second selection component, the second memory cell being different from the first memory cell, wherein the data is transferred from the first memory cell to the second memory cell based at least in part on receiving the first signal comprising the first read request for the first memory cell;
receiving, from the controller, a second signal comprising a second read request for the first memory cell, the second signal comprising the second read request being different from the first signal comprising the first read request, wherein the second signal comprising the second read request is received from the controller after the first signal comprising the first read request; and
reading, in response to the second read request, the data from the second memory cell based at least in part on transferring the data from the first memory cell to the second memory cell.
2. The method of claim 1 , further comprising:
receiving a read request for a third memory cell that comprises a second ferroelectric capacitor;
transferring second data from the third memory cell to a fourth memory cell that comprises a second paraelectric capacitor, wherein the second data is transferred from the third memory cell to the fourth memory cell based at least in part on receiving the read request of the third memory cell; and
directing a read attempt of the third memory cell to the fourth memory cell based at least in part on transferring the second data from the third memory cell to the fourth memory cell.
3. The method of claim 1 , wherein the first memory cell and the second memory cell comprise a memory cell pair of a memory array, the memory array comprising a plurality of ferroelectric memory cells and a plurality of paraelectric memory cells.
4. A method of operating a memory device, comprising:
receiving, at a controller, an indication to transfer at least one logic value between a first memory cell of a first cell type and a second memory cell of a second cell type, the first memory cell being different from the second memory cell, wherein the first cell type comprises a ferroelectric capacitor and a first selection component and the second cell type comprises a paraelectric capacitor and a second selection component different from the first selection component, wherein a substrate comprises the first memory cell and the second memory cell and comprises a first memory array comprising memory cells of the first cell type and a second memory array comprising memory cells of the second cell type, and wherein a quantity of memory cells of the first memory array is greater than a quantity of memory cells of the second memory array;
transferring the at least one logic value between the first memory cell and the second memory cell based at least in part on the received indication, wherein transferring the at least one logic value comprises transferring a subset of logic values between the first memory array and the second memory array;
receiving, at the controller, a request to read the at least one logic value from the first memory cell or the second memory cell; and
reading the at least one logic value from the first memory cell or the second memory cell based at least in part on transferring the at least one logic value between the first memory cell and the second memory cell.
5. The method of claim 4 , wherein receiving the indication to transfer the at least one logic value comprises:
receiving the indication from a component external to the substrate.
6. The method of claim 4 , wherein transferring the at least one logic value further comprises:
reading the at least one logic value stored in the first memory cell; and
writing the at least one logic value to the second memory cell.
7. The method of claim 4 , wherein transferring the at least one logic value further comprises:
reading the at least one logic value stored in the second memory cell; and
writing the at least one logic value to the first memory cell.
8. The method of claim 4 , wherein the substrate comprises a memory array that comprises the first memory cell and the second memory cell.
9. The method of claim 4 , wherein transferring the at least one logic value comprises:
transferring logic values stored in the second memory array to the first memory array based at least in part on a power interruption to the second memory array.
10. The method of claim 4 , wherein the indication to transfer the at least one logic value between the first memory cell and the second memory cell is based at least in part on a device comprising the memory device is powering down.
11. The method of claim 4 , wherein the first cell type comprises a non-volatile memory cell and the second cell type comprises a volatile memory cell.
12. An apparatus, comprising:
a substrate comprising a first memory cell of a first cell type and a second memory cell of a second cell type, the first memory cell being different from the second memory cell, wherein the substrate comprises a first memory array comprising memory cells of the first cell type and a second memory array comprising memory cells of the second cell type, and wherein a quantity of memory cells of the first memory array is greater than a quantity of memory cells of the second memory array; and
a controller in electronic communication with the substrate, wherein the controller is operable to cause the apparatus to:
receive an indication to transfer at least one logic value between the first memory cell of the first cell type and the second memory cell of the second cell type, wherein the first cell type comprises a ferroelectric capacitor and a first selection component and the second cell type comprises a paraelectric capacitor and a second selection component different from the first selection component;
transfer the at least one logic value between the first memory cell and the second memory cell based at least in part on the received indication;
transfer a subset of logic values between the first memory array and the second memory array;
receive a request to read the at least one logic value from the first memory cell or the second memory cell; and
read the at least one logic value from the first memory cell or the second memory cell based at least in part on transferring the at least one logic value between the first memory cell and the second memory cell.
13. The apparatus of claim 12 , wherein the controller is operable to cause the apparatus to:
receive the indication from a component external to the substrate.
14. The apparatus of claim 12 , wherein the controller is operable to cause the apparatus to:
read the at least one logic value stored in the first memory cell; and
write the at least one logic value to the second memory cell.
15. The apparatus of claim 12 , wherein the controller is operable to cause the apparatus to:
read the at least one logic value stored in the second memory cell; and
write the at least one logic value to the first memory cell.
16. The apparatus of claim 12 , wherein the controller is operable to cause the apparatus to:
transfer logic values stored in the second memory array to the first memory array based at least in part on a power interruption to the second memory array.