Memory cells programmed via multi-mechanism charge transports
Memory cells programmed via multi-mechanism charge transports are described herein. An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.
1. A method, comprising:
programming a memory cell to a target state via a multi-mechanism charge transport such that charges are simultaneously transported to a charge trapping material through a plurality of different channels; and
wherein programming the memory cells to the target state comprises transporting holes from a metal gate to the charge trapping material simultaneously with transporting holes from the semiconductor material to the charge trapping material; and
wherein the charge trapping material comprises gallium nitride (GaN).
2. The method of claim 1 , wherein the charge trapping material is formed on a tunneling material that is formed on a semiconductor material, and wherein the tunneling material comprises:
a first sub-material formed on the semiconductor material, the first sub-material comprising oxygen-rich silicon oxynitride (OR-SiON);
a second sub-material formed on the first sub-material, the second sub-material comprising lanthanum oxide (La 2 O 3 ); and
a third sub-material formed on the second sub-material, the third sub-material comprising hafnium dioxide (HfO 2 ).
3. The method of claim 1 , further comprising:
programming the memory cell to a data state other than an erased state by:
transporting electrons from a semiconductor material to the charge trapping material via a direct tunneling simultaneously with transporting electrons from the semiconductor material to the charge trapping material via a Fowler-Nordheim tunneling (F-N).
4. The method of claim 1 , further comprising:
programming the memory cell to a data state other than an erased state by:
transporting electrons from a semiconductor material to the charge trapping material via a direct tunneling simultaneously with transporting electrons from a source region to the charge trapping material.
5. A method, comprising:
programming a memory cell via a multi-mechanism charge transport, wherein:
the memory cell comprises a first charge trapping material and a second charge trapping material;
at least one of the first and the second charge trapping materials comprises gallium nitride (GaN); and
the first charge trapping material is formed closer to a semiconductor material than the second charge trapping material; and
transporting, via the multi-mechanism charge transport, electrons from the semiconductor material to the first charge trapping material via a direct tunneling simultaneously with transporting electrons from the semiconductor material to the second charge trapping material via a Fowler-Nordheim (F-N) tunneling;
wherein the method further comprises programming the memory cell to a second data state by:
transporting electrons from the semiconductor material to the first charge trapping material via the direct tunneling simultaneously with:
transporting electrons from the semiconductor material to the second charge trapping material via the F-N tunneling; and
transporting holes from the control gate to the second charge trapping material.
6. The method of claim 5 , wherein:
the first charge trapping material comprises GaN; and
the second charge trapping material comprises aluminum nitride (AlN).
7. The method of claim 5 , further comprising:
programming the memory cell to:
a first data state by applying a first voltage;
a second data state by applying a second voltage; and
a third data state by applying a third voltage; and
wherein the first, second, and third voltages are different.
8. The method of claim 7 , further comprising:
applying the third voltage to cause a threshold voltage to be greater than another threshold voltage caused by the second voltage due to holes transported from the control gate to the second trapping material; and
wherein the second voltage is greater than the first and the third voltages.
9. The method of claim 5 , further comprising:
programming the memory cell to a first data state by:
transporting electrons from the semiconductor material to the first charge trapping material via the direct tunneling.
10. The method of claim 5 , further comprising:
programming the memory cell to a third data state by:
transporting electrons from the semiconductor material to the first charge trapping material via the direct tunneling simultaneously with transporting electrons from the semiconductor material to the second charge trapping material via the F-N tunneling.
11. The method of claim 5 , further comprising programming the memory cell to an erased state by applying a negative voltage.
12. A method, comprising:
programming a memory cell to a target state via a multi-mechanism charge transport such that charges are simultaneously transported to a charge trapping material through a plurality of different channels; and
wherein the charge trapping material comprises gallium nitride (GaN); and
wherein the charge trapping material is formed on a tunneling material that is formed on a semiconductor material, and wherein the tunneling material comprises:
a first sub-material formed on the semiconductor material, the first sub-material comprising oxygen-rich silicon oxynitride (OR-SiON);
a second sub-material formed on the first sub-material, the second sub-material comprising lanthanum oxide (La 2 O 3 ); and
a third sub-material formed on the second sub-material, the third sub-material comprising hafnium dioxide (HfO 2 ).
13. A method, comprising:
programming a memory cell via a multi-mechanism charge transport, wherein:
the memory cell comprises a first charge trapping material and a second charge trapping material;
at least one of the first and the second charge trapping materials comprises gallium nitride (GaN); and
the first charge trapping material is formed closer to a semiconductor material than the second charge trapping material; and
transporting, via the multi-mechanism charge transport, electrons from the semiconductor material to the first charge trapping material via a direct tunneling simultaneously with transporting electrons from the semiconductor material to the second charge trapping material via a Fowler-Nordheim (F-N) tunneling;
wherein the method further comprises:
programming the memory cell to a first data state by applying a first voltage, a second data state by applying a second voltage, and a third data state by applying a third voltage, wherein the first, second, and third voltages are different; and
applying the third voltage to cause a threshold voltage to be greater than another threshold voltage caused by the second voltage due to holes transported from the control gate to the second trapping material, wherein the second voltage is greater than the first and the third voltages.