Asymmetric source/drain regions of transistors
An example apparatus includes a first transistor and a second transistor, each having asymmetric source/drain regions. A source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor at a junction. A depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor.
1. An apparatus, comprising:
a first transistor and a second transistor, each having asymmetric source/drain regions, wherein:
a source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor to form a junction;
a depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor;
the other source/drain regions of the first and second transistors have a same depth of a doping of a substrate material as a depth of a doping of the substrate material at the junction; and
the other source/drain regions of the first and second transistors are higher within the substrate material than the junction.
2. The apparatus of claim 1 , wherein the junction includes a deeper doping of a substrate material than a doping of the substrate material of the other source/drain regions of the first and second transistors.
3. The apparatus of claim 1 , wherein the junction is located in a trench in the substrate material.
4. The apparatus of claim 1 , wherein the depth of the junction is a depth of gates of the first and second transistors into a substrate material.
5. A method, comprising:
forming a trench in a substrate material between adjacent gates of a first transistor and a second transistor; and
doping, in a single doping operation, the substrate material to a same depth to form first source/drain regions of a first transistor and a second transistor and a junction of a second source/drain region of the first transistor and a second source/drain region of the second transistor, wherein the junction is located at the trench in the substrate material; a depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor,
wherein the first source/drain regions of the first and second transistors have a same depth of doping of the substrate material as the second source/drain regions of the first and second transistors, and
wherein the first source/drain regions of the first and second transistors are higher within the substrate material than the junction.
6. The method of claim 5 , wherein forming the trench includes performing an etching operation on the substrate material between the gates of the first and second transistors.
7. The method of claim 5 , wherein doping the substrate material in the single doping operation includes:
doping the substrate material to a first doping concentration at a surface of the substrate material and to a second doping concentration at a first depth relative to the surface of the substrate material; and
doping the substrate material between the gates of the first and second transistors to the first doping concentration at a bottom of the trench and to the second doping concentration at a depth relative to the bottom of the trench.
8. The method of claim 5 , wherein:
a plurality of pairs of the adjacent gates are formed in the substrate material; and
the method further comprises:
performing an etching operation on a respective portion of the substrate material between each respective pair of the adjacent gates to form a respective trench between each pair of the adjacent gates; and
performing the single doping operation on the substrate material subsequent to performing the etching operation.
9. The method of claim 5 , further comprising forming a conductive contact in the trench to electrically couple the second source/drain region of the first transistor to the second source/drain region of the second transistor at the junction.
10. The method of claim 5 , further comprising receiving control inputs to:
control at least one dimension of the trench in the substrate material between the gates of the first and second transistors; and
control the depth of the doping of the substrate material.
11. A system, comprising:
a memory device including a first transistor and a second transistor, each having asymmetric source/drain regions, wherein:
a source/drain region of the first transistor is directly coupled to a source/drain region of the second transistor to form a junction;
a depth of the junction is greater than a depth of another source/drain region of the first transistor and a depth of another source/drain region of the second transistor;
the other source/drain regions of the first and second transistors have a same depth of a doping of a substrate material as a depth of a doping of the substrate material at the junction; and
the other source/drain regions of the first and second transistors are higher within the substrate material than the junction.
12. The system of claim 11 , wherein:
the memory device includes a memory array including the first and second transistors; and
the first and second transistors are access transistors of the memory array.
13. The system of claim 12 , wherein the memory array includes:
a first dynamic random access memory (DRAM) cell including the first transistor; and
a second DRAM cell, adjacent to the first DRAM cell, including the second transistor.
14. The system of claim 12 , wherein each of the first and second transistors is a recessed access device (RAD).