Protection against timing-based security attacks by randomly adjusting reorder buffer capacity

1. A method, comprising:

executing, in a processor, instructions of an application according to an order different from an order in which the instructions are programmed;

buffering, in a re-order buffer of the processor, results of the instructions executed in the processor;

outputting, from the re-order buffer, the results of the instructions in accordance with the order in which the instructions are programmed;

adjusting, by the processor, a capacity of the re-order buffer in buffering the results;

generating a random number to determine the adjusted capacity, wherein the random number is configured to indicate a random fraction of a full capacity of the re-order buffer as a current capacity used to buffer the results; and

writing the results from the re-order buffer to registers according to the programmed order of the instructions of the application.

2. The method of claim 1 , wherein the capacity of the re-order buffer is adjusted from a predetermined full capacity to a first adjusted capacity, wherein during a time period of operation of the re-order buffer, the first adjusted capacity limits an amount of results bufferable in the re-order buffer.

3. The method of claim 1 , further comprising:

operating the re-order buffer at the adjusted capacity during a first period of time;

determining a further adjusted capacity for a second period of time following the first period of time; and

operating the re-order buffer at the further adjusted capacity during the second period of time.

4. The method of claim 3 , wherein the second period of time and the first period of time have different lengths.

5. The method of claim 1 , further comprising:

fetching the instructions according to the order in which the instructions are programmed;

buffering the instructions in an instruction buffer; and

issuing the instructions to functional units of the processor in accordance with an order in which operands of the instructions become available in the functional units.

6. A processor, comprising:

one or more functional units configured to execute instructions of an application;

a re-order buffer configured to buffer results of the instructions executed in the one or more functional units out of order relative to a programmed order of the instructions of the application;

a controller configured to dynamically adjust a capacity of the re-order buffer, periodically;

registers, wherein the processor is configured to write the results from the re-order buffer to the registers according to the programmed order of the instructions of the application; and

a random number generator, wherein the controller is configured to determine the capacity based on an output of the random number generator;

wherein the output of the random number generator indicates a random fraction of a full capacity of the re-order buffer as a current capacity used to buffer the results.

7. The processor of claim 6 , wherein the controller is configured to update the random fraction periodically to control current usage of the re-order buffer.

8. The processor of claim 6 , wherein the controller is configured to update the random fraction after a random time period to control current usage of the re-order buffer.

9. The processor of claim 6 , wherein the controller is configured to change a timing pattern in results generated by a set of instructions and stored in the re-order buffer by adjusting the capacity usable in re-ordering results.

10. The processor of claim 9 , further comprising:

an instruction buffer, wherein the processor is configured to fetch instructions into the instruction buffer in accordance with an order in which the fetched instructions are programmed and issue instructions from the instruction buffer to the one or more functional units in accordance with an order in which operands of instructions in the instruction buffer are ready in the one or more functional units.

11. A non-transitory computer readable medium storing a first set of instructions which, when executed in a processor, cause the processor to perform a method, the method comprising:

executing, in the processor, a second set of instructions of an application according to an order different from an order in which the second set of instructions are programmed;

buffering, in a re-order buffer of the processor, results of the second set of instructions executed in the processor;

outputting, from the re-order buffer, the results of the second set of instructions in accordance with the order in which the second set of instructions are programmed;

adjusting operations of the re-order buffer to introduce randomness in a timing pattern in results that are generated by a set of instructions and stored in the re-order buffer, wherein the adjusting includes changing a current operational capacity of the re-order buffer based on a random number, wherein the current operational capacity is reduced from a full capacity of the re-order buffer to a first adjusted capacity;

generating the random number to determine the first adjusted capacity, wherein the random number is configured to indicate a random fraction of a full capacity of the re-order buffer as a current capacity used to buffer the results of the second set of instructions; and

writing the results from the re-order buffer to registers according to the programmed order of the second set of instructions of the application.

12. The non-transitory computer readable medium of claim 11 ,

wherein the method further comprises:

determining a random time period during which the re-order buffer is operated at the current operational capacity.

13. The non-transitory computer readable medium of claim 12 ,

wherein the method further comprises:

fetching the second set of instructions according to the order in which the second set of instructions are programmed;

buffering the second set of instructions in an instruction buffer; and

issuing the second set of instructions to functional units of the processor in accordance with an order in which operands of the second set of instructions become available in the functional units.