IP Library Granted Patent US 10,937,798
Granted Patent B2
US 10,937,798 · App. 16/179,572 · Granted Mar 2, 2021

Memory array and a method used in forming a memory array

Inventors: Changhan Kim (Boise, ID); Richard J. Hill (Boise, ID); John D. Hopkins (Meridian, ID); Collin Howder (Meridian, ID)
Assignee: Micron Technology, Inc.
H01L27/11582H01L27/1157H01L27/11524H01L27/11556H01L29/40114H01L29/40117
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Quick Facts
Patent No.
US 10,937,798
App. No.
16/179,572
Granted
Mar 2, 2021
Kind
B2
Abstract

A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

Claims (54)

1. A method used in forming a memory array, comprising:

forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the insulative tiers and the wordline tiers comprising opposing longitudinal edges comprising longitudinal shape of longitudinal outlines of individual wordlines to be formed in individual of the wordline tiers, the wordline tiers comprising a first material, the insulative tiers comprising a second material of different composition from that of the first material;

removing a top portion and a bottom portion of the second material at the longitudinal edges of the insulative tiers to form upper and lower recesses in the second material; and

forming conductive material in the upper and lower recesses, the conductive material projecting upwardly and downwardly into individual of the insulative tiers and comprising a portion of the individual wordlines, the individual wordlines being formed to comprise opposing laterally-outer longitudinal edges, the laterally-outer longitudinal edges individually comprising a longitudinally-elongated recess that extends laterally inward into the respective individual wordline.

2. The method of claim 1 comprising removing all remaining of the first material from the wordline tiers before the forming of the conductive material.

3. The method of claim 1 comprising removing all remaining of the first material from the wordline tiers after the removing of the top portion and the bottom portion.

4. The method of claim 1 comprising removing all remaining of the first material from the wordline tiers after the removing of the top portion and the bottom portion and before the forming of the conductive material.

5. The method of claim 1 comprising removing all remaining of the second material from the insulative tiers after forming the conductive material.

6. The method of claim 1 wherein the removing of the top portion and a bottom portion of the second material at the longitudinal edges of the insulative tiers to form upper and lower recesses in the second material comprises etching.

7. The method of claim 1 wherein the removing comprises isotropic etching of the top portion and the bottom portion selectively relative to the second material.

8. The method of claim 1 comprising forming insulator material to extend elevationally completely between upwardly and downwardly projecting portions of the upwardly and downwardly projecting conductive material of immediately vertically adjacent of the wordline tiers.

9. The method of claim 8 wherein the forming of the insulator material forms longitudinally-elongated sealed voids in individual of the insulative tiers.

10. The method of claim 1 comprising:

forming the memory array to comprise individual memory cells;

forming channel material to extend elevationally through the insulative tiers and the wordline tiers; and

forming the individual memory cells to comprise a gate region and a memory structure laterally between the gate region and the channel material.

11. The method of claim 10 comprising forming the memory structure to comprise:

a charge-blocking region of the individual memory cells elevationally along the individual gate regions;

charge-storage material of the individual memory cells elevationally along individual of the charge-blocking regions; and

insulative charge-passage material laterally between the channel material and the charge-storage material.

12. A method used in forming a memory array, comprising:

forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the insulative tiers and the wordline tiers comprising opposing longitudinal edges comprising longitudinal shape of longitudinal outlines of individual wordlines to be formed in individual of the wordline tiers, the wordline tiers comprising a first sacrificial material, the insulative tiers comprising a second material of different composition from that of the first sacrificial material;

laterally recessing the first sacrificial material from the opposing longitudinal edges of the insulative tiers and from the second material thereof;

isotropically etching exposed top and bottom portions of the second material at the longitudinal edges of the insulative tiers to form upper and lower recesses in the second material, remaining portions of the first sacrificial material masking the second material during and from the isotropically etching;

removing the first sacrificial material after the isotropically etching to form wordline-tier voids; and

forming conductive material in the wordline-tier voids and in the upper and lower recesses, the conductive material in the upper and lower recesses projecting downwardly and upwardly, respectively, into individual of the insulative tiers, the conductive material in the wordline-tier voids and in the upper and lower recesses comprising the individual wordlines, the individual wordlines being formed to comprise opposing laterally-outer longitudinal edges, the laterally-outer longitudinal edges individually comprising a longitudinally-elongated recess that extends laterally inward into the respective individual wordline.

13. The method of claim 12 wherein the removing of the first sacrificial material after the isotropically etching to form the wordline-tier voids is conducted selectively relative to the second material.

14. The method of claim 12 comprising forming insulator material to extend elevationally completely between upwardly and downwardly projecting portions of the upwardly and downwardly projecting conductive material of immediately vertically adjacent of the wordline tiers.

15. The method of claim 14 wherein the forming of the insulator material forms longitudinally-elongated sealed voids in the individual insulative tiers.

16. A method used in forming a memory array, comprising:

forming a stack comprising vertically-alternating insulative tiers and wordline tiers, the insulative tiers and the wordline tiers comprising opposing longitudinal edges comprising longitudinal shape of longitudinal outlines of individual wordlines to be formed in individual of the wordline tiers, the wordline tiers comprising a first sacrificial material, the insulative tiers and the opposing longitudinal edges thereof comprising a second sacrificial material of different composition from that of the first sacrificial material;

laterally recessing the first sacrificial material from the opposing longitudinal edges of the insulative tiers and from the second sacrificial material thereof;

after the laterally recessing, isotropically etching exposed top and bottom portions of the second sacrificial material at the longitudinal edges of the insulative tiers to form upper and lower recesses in the second sacrificial material, remaining portions of the first sacrificial material masking the second sacrificial material during and from the isotropically etching;

after isotropically etching the exposed top and bottom portions of the second sacrificial material, removing the first sacrificial material selectively relative to the second sacrificial material to form wordline-tier voids;

forming conductive material in the wordline-tier voids and in the upper and lower recesses, the conductive material in the upper and lower recesses projecting downwardly and upwardly, respectively, into individual of the insulative tiers, the conductive material in the wordline-tier voids and in the upper and lower recesses comprising the individual wordlines, the conductive material covering the opposing longitudinal edges of the second sacrificial material of the insulative tiers;

laterally etching back the conductive material to uncover the opposing longitudinal edges of the second sacrificial material of the insulative tiers;

removing the second sacrificial material selectively relative to the conductive material to form the insulative tiers to individually comprise longitudinally-elongated voids;

forming insulator material to extend elevationally completely between upwardly and downwardly projecting portions of the conductive material that is in the upper and lower recesses and to seal-up the longitudinally-elongated voids; and

the individual wordlines being formed to comprise opposing laterally-outer longitudinal edges, the laterally-outer longitudinal edges individually comprising a longitudinally-elongated recess that extends laterally inward into the respective individual wordline.

17. The method of claim 16 wherein the laterally etching back removes some and only some of the conductive material from the upper recesses and from the lower recesses.

18. The method of claim 1 wherein a deepest lateral extent of the longitudinally-elongated recess is vertically centered relative to the respective individual wordline.

19. The method of claim 1 wherein the longitudinally-elongated recess has a laterally-outermost surface in a vertical cross-section extending from a top to a bottom of its wordline and that is curved from said top to said bottom.

20. The method of claim 1 wherein,

the longitudinally-elongated recess has a laterally-outermost surface in a vertical cross-section extending from a top to a bottom of its wordline and that is curved from said top to said bottom; and

a deepest lateral extent of the longitudinally-elongated recess is vertically centered relative to the respective individual wordline.

21. The method of claim 12 wherein a deepest lateral extent of the longitudinally-elongated recess is vertically centered relative to the respective individual wordline.

22. The method of claim 12 wherein the longitudinally-elongated recess has a laterally-outermost surface in a vertical cross-section extending from a top to a bottom of its wordline and that is curved from said top to said bottom.

23. The method of claim 12 wherein, the longitudinally-elongated recess has a laterally-outermost surface in a vertical cross-section extending from a top to a bottom of its wordline and that is curved from said top to said bottom; and

a deepest lateral extent of the longitudinally-elongated recess is vertically centered relative to the respective individual wordline.

24. The method of claim 16 wherein a deepest lateral extent of the longitudinally-elongated recess is vertically centered relative to the respective individual wordline.

25. The method of claim 16 wherein the longitudinally-elongated recess has a laterally-outermost surface in a vertical cross-section extending from a top to a bottom of its wordline and that is curved from said top to said bottom.

26. The method of claim 16 wherein,

the longitudinally-elongated recess has a laterally-outermost surface in a vertical cross-section extending from a top to a bottom of its wordline and that is curved from said top to said bottom; and

a deepest lateral extent of the longitudinally-elongated recess is vertically centered relative to the respective individual wordline.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2018
From: KIM, CHANGHAN; HILL, RICHARD J.; HOPKINS, JOHN D.; HOWDER, COLLIN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047398/0636 →
Continuity (1)
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