IP Library Granted Patent US 11,101,014
Granted Patent B2
US 11,101,014 · App. 16/353,966 · Granted Aug 24, 2021

Two-stage flash programming for embedded systems

Inventor: Gil Golov (Backnang, DE)
Assignee: Micron Technology, Inc.
G11C29/12G06F8/63G06F11/22G06F11/2284G11C11/5628
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Quick Facts
Patent No.
US 11,101,014
App. No.
16/353,966
Granted
Aug 24, 2021
Kind
B2
Abstract

Disclosed are devices and methods for improving the initialization of devices housing memories. In one embodiment, a method is disclosed comprising writing a test program to a first region of a memory device during production of the memory device; executing a self-test program in response to detecting a first power up of the memory device, the self-test program stored within the test program; and retrieving and installing an image from a remote data source in response to detecting a subsequent power up of the memory device, the retrieving performed by the test program.

Claims (21)

1. A method comprising: writing a test program to a first region of a memory device during production of the memory device; executing a self-test program in response to detecting a first power up of the memory device, the self-test program stored within the test program; and retrieving and installing an image from a remote data source in response to detecting a subsequent power up, during an installation process of the memory device, the retrieving performed by the test program.

2. The method of claim 1 , further comprising detecting that the memory device is connected to a bus upon detecting the subsequent power up.

3. The method of claim 1 , the retrieving the image comprising establishing communications with a production line server, the production line server storing one or more images including the image.

4. The method of claim 1 , the writing a test program comprising writing the test program after soldering the memory device to a printed circuit board.

5. The method of claim 1 , the writing a test program including one or more communications drivers and self-programming software.

6. The method of claim 1 , further comprising running an integrity test on the installed image.

7. The method of claim 1 , the retrieving the image comprising retrieving the image using an over-the-air network.

8. A device comprising: a microcontroller; and a non-transitory computer readable storage medium for tangibly storing thereon program instructions for execution by the processor, the stored program instructions comprising a test program written to a first region of a memory device during production of the memory device, the test program configured to: execute a self-test program stored within the test program in response to detecting a first power up of the memory device; and retrieve and install an image from a remote data source in response to detecting a subsequent power up, during an installation process of the memory device, the retrieving performed by the test program.

9. The device of claim 8 , the test program further configured to detect that the device is connected to a bus upon detecting the subsequent power up.

10. The device of claim 8 , the retrieving the image comprising establishing communications with a production line server, the production line server storing one or more images including the image.

11. The device of claim 8 , the writing a test program comprising writing the test program after soldering the memory device to a printed circuit board.

12. The device of claim 8 , the writing a test program including one or more communications drivers and self-programming software.

13. The device of claim 8 , the test program further configured to run an integrity test on the installed image.

14. The device of claim 8 , the retrieving the image comprising retrieving the image using an over-the-air network.

15. A non-transitory computer readable storage medium for tangibly storing computer program instructions capable of being executed by a computer processor, the computer program instructions defining the steps of: writing a test program to a first region of a memory device during production of the memory device; executing a self-test program in response to detecting a first power up of the memory device, the self-test program stored within the test program; and retrieving and installing an image from a remote data source in response to detecting a subsequent power up, during an installation process of the memory device, the retrieving performed by the test program.

16. The non-transitory computer readable storage medium of claim 15 , the computer program instructions further defining the step of detecting that the memory device is connected to a bus upon detecting the subsequent power up.

17. The non-transitory computer readable storage medium of claim 15 , the retrieving the image comprising establishing communications with a production line server, the production line server storing one or more images including the image.

18. The non-transitory computer readable storage medium of claim 15 , the writing a test program comprising writing the test program after soldering the memory device to a printed circuit board.

19. The non-transitory computer readable storage medium of claim 15 , the writing a test program including one or more communications drivers and self-programming software.

20. The non-transitory computer readable storage medium of claim 15 , the computer program instructions further defining the step of running an integrity test on the installed image.

21. The non-transitory computer readable storage medium of claim 15 , the retrieving the image comprising retrieving the image using an over-the-air network.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2019
From: GOLOV, GIL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 048837/0885 →