IP Library Granted Patent US 10,838,812
Granted Patent B2
US 10,838,812 · App. 16/190,006 · Granted Nov 17, 2020

Storing parity data mid stripe

Inventor: Daniel A. Boals (Broomfield, CO)
Assignee: Micron Technology, Inc.
G06F11/1076G06F3/064G06F3/0619G06F3/0679
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,838,812
App. No.
16/190,006
Granted
Nov 17, 2020
Kind
B2
Abstract

User data to be stored at a data block location of a plurality of data block locations at a storage system may be received. A parity data based on the received user data may be generated. An indication of an occurrence of an event associated with the storage system may be received. In response to receiving the indication of the occurrence of the event, the parity data may be stored by a processing device at a particular data block location of the plurality of data block locations where the particular data block location is situated prior to another data block location, of the plurality of data block locations, that is to store another parity data based on a subsequent user data.

Claims (45)

1. A method comprising:

identifying a first data block location that is predetermined to store a first parity data based on a plurality of user data at a plurality of data block locations of a storage system;

storing a set of user data at a subset of data block locations of the plurality of data block locations;

storing a second parity data at a memory buffer location, wherein the second parity data is generated based on the set of user data;

receiving an indication of an occurrence of an event associated with the storage system;

in response to receiving the indication of the occurrence of the event, storing, by a processing device, the second parity data at a second data block location of the plurality of data block locations, wherein the second data block location is situated after the subset of the plurality of data block locations and prior to the first data block location; and

replacing the second parity data in the memory buffer with an initial value of a default hardware initialization state of the storage system to allow for calculating additional parity data based on the initial value and additional user data to be stored in one or more data block locations situated after the second data block location.

2. The method of claim 1 , wherein the plurality of data block locations corresponds to a single data block stripe.

3. The method of claim 1 wherein the initial value of the default hardware initialization state is zero.

4. The method of claim 1 , further comprising:

generating the first parity data based on the initial value of the default hardware initialization state and the additional user data stored in data block locations situated between the second data block location and the first data block location; and

storing the first parity data in the first data block location.

5. The method of claim 1 , wherein the first data block location is situated at the end of the plurality of data block locations.

6. The method of claim 1 , wherein the event corresponds to a power loss associated with the storage system.

7. The method of claim 1 , wherein the event corresponds to a hardware limitation associated with the storage system.

8. The method of claim 1 , wherein the first parity data and the second parity data are used to recover a user data stored at one of the data block locations of the plurality of data block locations.

9. A system comprising:

a memory;

a processing device, operatively coupled with the memory, to:

identify a series of data block locations to store a series of data at a storage system;

identify a first data block location in the series of data block locations that is predetermined to store a first parity data based on a plurality of user data at the series of data block locations;

select a second data block location of the series of data block locations to store a particular user data of the series of data, wherein the second data block location is situated prior to the first data block location in the series of data block locations;

store a second parity data at a memory buffer location in view of user data that has been stored in the series of data block locations prior to the second data block location;

receive an indication of an event associated with the storage system;

in response to receiving the indication, store the second parity data at the second data block location; and

replace the second parity data in the memory buffer with an initial value of a default hardware initialization state of the storage system to allow for calculating additional parity data based on the initial value and additional user data to be stored in one or more data block locations of the series of data block locations after the second data block location.

10. The system of claim 9 , wherein the series of data block locations comprises a single data block stripe.

11. The system of claim 9 wherein the initial value of the default hardware initialization state is zero.

12. The system of claim 9 , wherein the processing device is further to:

generate the first parity data based on the initial value of the default hardware initialization state and the additional user data stored in the series of data block locations situated between the second data block location and the first data block location; and

store the first parity data in the first data block location.

13. The system of claim 9 , wherein the first data block location is situated at the end of the series of data block locations.

14. The system of claim 9 , wherein the event corresponds to a power loss associated with the storage system.

15. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

identifying a first data block location that is predetermined to store a first parity data based on a plurality of user data at a plurality of data block locations of a storage system;

storing a set of user data at a subset of data block locations of the plurality of data block locations;

storing a second parity data at a memory buffer location, wherein the second parity data is generated based on the set of user data;

receiving an indication of an occurrence of an event associated with the storage system;

in response to receiving the indication of the occurrence of the event, storing the second parity data at a second data block location of the plurality of data block locations, wherein the second data block location is situated after the subset of the plurality of data block locations and prior to the first data block location, of the plurality of data block locations; and

replacing the second parity data in the memory buffer with an initial value of a default hardware initialization state of the storage system to allow for calculating additional parity data based on the initial value and additional user data to be stored in one or more data block locations situated after the second data block location.

16. The non-transitory computer-readable medium of claim 15 , wherein the plurality of data block locations corresponds to a single data block stripe.

17. The non-transitory computer-readable medium of claim 15 wherein the initial value of the default hardware initialization state is zero.

18. The non-transitory computer-readable medium of claim 17 , wherein the first data block location is situated at the end of the plurality of data block locations.

19. The non-transitory computer-readable medium of claim 15 , wherein the event corresponds to a power loss associated with the storage system.

20. The non-transitory computer-readable medium of claim 15 , wherein the event corresponds to a hardware limitation associated with the storage system.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 051041/0317 →
RELEASE OF SECURITY INTEREST Recorded Oct 14, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050724/0392 →
SUPPLEMENT NO. 12 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 048948/0677 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Apr 19, 2019
From: MICRON TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 048951/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2018
From: BOALS, DANIEL A.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047491/0779 →
Continuity (1)
Related Publication 20200151059A1 · May 14, 2020